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Datasheet > CDCVF2510PWRG4
CDCVF2510PWRG4 PDF预览

CDCVF2510PWRG4

更新时间： 2024-11-18 21:17:47
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
16页 767K
描述
3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85

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CDCVF2510PWRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP24,.25
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.22
系列：2510输入调节：STANDARD
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm负载电容（CL）：25 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：10最高工作温度：85 °C
最低工作温度：输出特性：SERIES-RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：3.9 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.1 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最小 fmax：175 MHz
Base Number Matches：1

CDCVF2510PWRG4 数据手册

 浏览型号CDCVF2510PWRG4的Datasheet PDF文件第2页浏览型号CDCVF2510PWRG4的Datasheet PDF文件第3页浏览型号CDCVF2510PWRG4的Datasheet PDF文件第4页浏览型号CDCVF2510PWRG4的Datasheet PDF文件第5页浏览型号CDCVF2510PWRG4的Datasheet PDF文件第6页浏览型号CDCVF2510PWRG4的Datasheet PDF文件第7页 
CDCVF2510  
www.ti.com  
SCAS638C–JULY 2001–REVISED APRIL 2006  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
FEATURES  
PW PACKAGE  
(TOP VIEW)  
•
Designed to Meet and Exceed PC133 SDRAM  
Registered DIMM Specification Rev. 1.1  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
•
•
•
Spread Spectrum Clock Compatible  
V
CC  
2
CC  
Operating Frequency 50 MHz to 175 MHz  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
3
V
CC  
Static Phase Error Distribution at 66 MHz to  
166 MHz Is ±125 ps  
1Y9  
1Y8  
GND  
GND  
4
5
•
•
Jitter (cyc - cyc) at 66 MHz to 166 MHz  
Is |70| ps  
6
7
Advanced Deep Submicron Process Results  
in More Than 40% Lower Power Consumption  
Versus Current Generation PC133 Devices  
8
17 1Y7  
16 1Y6  
15 1Y5  
1Y4  
9
V
CC  
10  
11  
12  
•
•
Available in Plastic 24-Pin TSSOP  
G
V
CC  
14  
13  
FBOUT  
FBIN  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
•
•
Distributes One Clock Input to One Bank of  
10 Outputs  
NOT RECOMMENDED  
FOR NEW DESIGNS  
USE CDCVF2510A AS  
A REPLACEMENT  
External Feedback (FBIN) Terminal Is Used to  
Synchronize the Outputs to the Clock Input  
•
•
•
25-Ω On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
DESCRIPTION  
The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a  
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock  
(CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a  
3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to  
50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the  
G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are  
disabled to the logic-low state.  
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDCVF2510 requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required following power up and application of a  
fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals.  
The PLL can be bypassed for test purposes by strapping AVCC to ground.  
The CDCVF2510 is characterized for operation from 0°C to 85°C.  
For application information see the application reports High Speed Distribution Design Techniques for  
CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking  
(SSC) (SCAA039).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...16

中文翻译

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CDCVF2510PWRG4 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF2510PWR TI

完全替代

 适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 | PW |
CDCVF2510PW TI

类似代替

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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