CDCVF2509A

更新时间： 2024-11-18 09:21:19

品牌	Logo	应用领域
德州仪器 - TI		驱动时钟
页数	文件大小	规格书
12页	163K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

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CDCVF2509A 数据手册

CDCVF2509A

www.ti.com

SCAS765A–APRIL 2004–REVISED JULY 2004

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH POWER DOWN MODE

FEATURES

•

DRAM Applications

PLL Based Clock Distributors

Non-PLL Clock Buffer

•

Designed to Meet and Exceed PC133

SDRAM Registered DIMM Specification

Rev. 1.1

•

Spread Spectrum Clock Compatible

PW PACKAGE

(TOP VIEW)

Operating Frequency 20 MHz to 175 MHz

Static Phase Error Distribution at 66 MHz to

166 MHz Is ±125 ps

AGND

CLK

•

Jitter (cyc - cyc) at 66 MHz to 166 MHz Is

|70| ps

1Y0

1Y1

1Y2

GND

1Y3

2Y0

2Y1

GND

Advanced Deep Submicron Process

Results in More Than 40% Lower Power

Consumption Versus Current Generation

PC133 Devices

17 2Y2

16 2Y3

•

Auto Frequency Detection to Disable

Device (Power-Down Mode)

1Y4

•

Available in Plastic 24-Pin TSSOP

FBOUT

FBIN

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

•

Distributes One Clock Input to One Bank of

Five and One Bank of Four Outputs

Separate Output Enable for Each Output

Bank

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

•

25-Ω On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

DESCRIPTION

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is

specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V V_CC. It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or

disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase

and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. The device

automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a

low state.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...12

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与CDCVF2509A相关器件

型号	品牌	获取价格	描述	数据表
CDCVF2509APW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509PW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2509PWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510A	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APW	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510PW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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