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CDCVF2509APWR PDF预览

CDCVF2509APWR

更新时间： 2024-11-30 09:21:19
品牌 Logo 应用领域
德州仪器 - TI 驱动时钟
页数 文件大小 规格书
12页 163K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

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中文翻译

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CDCVF2509APWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.67
系列：2509输入调节：STANDARD
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：7.8 mm负载电容（CL）：25 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：9最高工作温度：85 °C
最低工作温度：输出特性：SERIES-RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3.9 ns传播延迟（tpd）：3.9 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.1 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：OTHER
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
最小 fmax：175 MHzBase Number Matches：1

CDCVF2509APWR 数据手册

 浏览型号CDCVF2509APWR的Datasheet PDF文件第2页浏览型号CDCVF2509APWR的Datasheet PDF文件第3页浏览型号CDCVF2509APWR的Datasheet PDF文件第4页浏览型号CDCVF2509APWR的Datasheet PDF文件第5页浏览型号CDCVF2509APWR的Datasheet PDF文件第6页浏览型号CDCVF2509APWR的Datasheet PDF文件第7页 
CDCVF2509A  
www.ti.com  
SCAS765A–APRIL 2004–REVISED JULY 2004  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
WITH POWER DOWN MODE  
FEATURES  
FEATURES  
•
•
•
DRAM Applications  
PLL Based Clock Distributors  
Non-PLL Clock Buffer  
•
Designed to Meet and Exceed PC133  
SDRAM Registered DIMM Specification  
Rev. 1.1  
•
•
•
Spread Spectrum Clock Compatible  
PW PACKAGE  
(TOP VIEW)  
Operating Frequency 20 MHz to 175 MHz  
Static Phase Error Distribution at 66 MHz to  
166 MHz Is ±125 ps  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
V
CC  
2
•
•
Jitter (cyc - cyc) at 66 MHz to 166 MHz Is  
|70| ps  
CC  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
3
V
CC  
2Y0  
2Y1  
GND  
GND  
4
Advanced Deep Submicron Process  
Results in More Than 40% Lower Power  
Consumption Versus Current Generation  
PC133 Devices  
5
6
7
8
17 2Y2  
16 2Y3  
•
Auto Frequency Detection to Disable  
Device (Power-Down Mode)  
1Y4  
9
V
CC  
10  
11  
12  
15  
14  
13  
V
CC  
•
•
Available in Plastic 24-Pin TSSOP  
1G  
FBOUT  
2G  
FBIN  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
•
•
•
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
Separate Output Enable for Each Output  
Bank  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
•
•
•
25-Ω On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
DESCRIPTION  
The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is  
specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V VCC. It also  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or  
disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase  
and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. The device  
automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a  
low state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...12

中文翻译

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CDCVF2509APWR 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF2509APW TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2509PW TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCLVP110VF TI

功能相似

 LOW-VOLTAGE 1:10 LVPECL/HSTL WITH SELECTABLE INPUT CLOCK DRIVER

与CDCVF2509APWR相关器件

型号 品牌 获取价格 描述 数据表
CDCVF2509PW TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2509PWR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510 TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510A TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APW TI

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 		3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510APWR TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APWRG4 TI

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 		3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510PW TI

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 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510PWLE TI

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 		暂无描述
CDCVF2510PWR TI

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 		适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 | PW |

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