CDCVF2510A

更新时间： 2024-10-01 22:28:55

品牌	Logo	应用领域
德州仪器 - TI		驱动时钟
页数	文件大小	规格书
13页	161K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

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CDCVF2510A 数据手册

CDCVF2510A

www.ti.com

SCAS764B–MARCH 2004–REVISED APRIL 2005

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH POWER DOWN MODE

FEATURES

APPLICATIONS

•

DRAM Applications

PLL Based Clock Distributors

Non-PLL Clock Buffer

•

Designed to Meet and Exceed PC133

SDRAM Registered DIMM Specification

Rev. 1.1

•

Spread Spectrum Clock Compatible

PW PACKAGE

(TOP VIEW)

Operating Frequency 20 MHz to 175 MHz

Static Phase Error Distribution at 66 MHz to

166 MHz is ±125 ps

AGND

CLK

•

Jitter (cyc–cyc) at 66 MHz to 166 MHz is

|70| ps

1Y0

1Y1

1Y2

GND

1Y3

1Y9

1Y8

GND

Advanced Deep Submicron Process Results

in More Than 40% Lower Power

Consumption vs Current Generation

PC133 Devices

17 1Y7

16 1Y6

15 1Y5

•

Auto Frequency Detection to Disable

Device (Power-Down Mode)

1Y4

•

Available in Plastic 24-Pin TSSOP

Distributes One Clock Input to One Bank of

10 Outputs

FBOUT

FBIN

•

External Feedback (FBIN) Terminal is

Used to Synchronize the Outputs to the Clock

Input

•

25-Ω On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3 V

DESCRIPTION

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The

CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback

(FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

CDCVF2510A operates at a 3.3-V V_CCand also provides integrated series-damping resistors that make it ideal

for driving point-to-point loads.

One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to

50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the

G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are

disabled to the logic-low state. The device automically goes into power-down mode when no input signal

(< 1 MHz) is applied to CLK; the outputs go into a low state.

Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application of a

fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals.

The PLL can be bypassed by strapping AV_CCto ground to use as a simple clock buffer.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...13

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与CDCVF2510A相关器件

型号	品牌	获取价格	描述	数据表
CDCVF2510APW	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE
CDCVF2510APWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver with Power Down Mode 24-TSSOP 0 to 85
CDCVF2510PW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF2510PWLE	TI	获取价格	暂无描述
CDCVF2510PWR	TI	获取价格	适用于 DRAM 应用且具有 10 个输出的 3.3V 锁相环路时钟驱动器 \| PW \|
CDCVF2510PWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85
CDCVF310	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310_15	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
CDCVF310PW	TI	获取价格	2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER

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