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CDC2536DLR PDF预览

CDC2536DLR

更新时间： 2024-09-15 20:04:55
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
15页 486K
描述
3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP

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CDC2536DLR 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP28,.4针数：28
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.72系列：2536
输入调节：STANDARDJESD-30 代码：R-PDSO-G28
长度：9.525 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A功能数量：1
反相输出次数：端子数量：28
实输出次数：6最高工作温度：70 °C
最低工作温度：输出特性：3-STATE WITH SERIES RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP28,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.5 ns座面最大高度：2.79 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
最小 fmax：100 MHzBase Number Matches：1

CDC2536DLR 数据手册

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CDC2536  
www.ti.com  
SCAS377E–APRIL 1994–REVISED JULY 2004  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS  
FEATURES  
DB PACKAGE  
(TOP VIEW)  
•
Low Output Skew for Clock-Distribution and  
Clock-Generation Applications  
AV  
AV  
AGND  
•
•
•
Operates at 3.3-V VCC  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CC  
CC  
AGND  
CLKIN  
SEL  
OE  
GND  
1Y1  
2
Distributes One Clock Input to Six Outputs  
FBIN  
TEST  
CLR  
3
One Select Input Configures Three Outputs to  
Operate at One-Half or Double the Input  
Frequency  
4
5
V
CC  
6
•
•
•
No External RC Network Required  
On-Chip Series Damping Resistors  
2Y1  
7
V
CC  
GND  
8
External Feedback Pin (FBIN) Is Used to  
Synchronize the Outputs to the Clock Input  
GND  
1Y2  
V
CC  
9
2Y2  
GND  
10  
11  
12  
13  
14  
V
CC  
•
Application for Synchronous DRAM,  
High-Speed Microprocessor  
GND  
1Y3  
V
CC  
2Y3  
•
•
TTL-Compatible Inputs and Outputs  
V
CC  
GND  
Outputs Drive 50-Ω Parallel-Terminated  
Transmission Lines  
•
•
•
State-of-the-Art EPIC-IIB™ BiCMOS Design  
Significantly Reduces Power Dissipation  
Distributed VCC and Ground Pins Reduce  
Switching Noise  
Packaged in Plastic 28-Pin Shrink  
Small-Outline Package  
DESCRIPTION  
The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to  
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is  
specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from  
50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536  
operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chip  
series-damping resistors, eliminating the need for external termination components.  
The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock  
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between  
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.  
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input  
configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fed  
back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty  
cycle at the input clock.  
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.  
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass  
the PLL. TEST should be strapped to GND for normal operation.  
Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter for  
the PLL is included on-chip, minimizing component count, board space, and cost.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-IIB is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1994–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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