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CDC304DR PDF预览

CDC304DR

更新时间: 2024-11-06 12:58:47
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
6页 91K
描述
1-To-8, Divide-By-2 Clock Driver With Preset And Clear 16-SOIC

CDC304DR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.91系列:304
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
长度:9.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.048 A功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):9 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):1 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mm最小 fmax:80 MHz
Base Number Matches:1

CDC304DR 数据手册

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CDC304  
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER  
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995  
D OR N PACKAGE  
(TOP VIEW)  
Replaces SN74AS304  
Maximum Output Skew of 1 ns  
Maximum Pulse Skew of 1.5 ns  
TTL-Compatible Inputs and Outputs  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q2  
Q1  
CLR  
Q3  
Q4  
GND  
GND  
GND  
Q5  
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
V
CC  
V
CC  
Package Options Include Plastic  
Small-Outline (D) Package and Standard  
Plastic (N) 300-mil DIPs  
CLK  
PRE  
Q8  
Q6  
Q7  
description  
The CDC304 contains eight flip-flops designed to have low skew between outputs. The eight outputs (in-phase  
with CLK) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q  
outputs high or low independent of the clock (CLK) input.  
The CDC304 has output and pulse-skew parameters t  
when a divide-by-two function is required.  
and t  
to ensure performance as a clock driver  
sk(o)  
sk(p)  
The CDC304 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
Q1Q8  
CLR  
L
PRE  
H
CLK  
X
L
H
L
X
H
L
L
L
X
H
H
Q
Q
0
0
H
H
L
This configuration does not persist  
when PRE or CLR returns to its  
inactive (high) level.  
logic symbol  
15  
Q1  
16  
Q2  
1
10  
11  
PRE  
CLK  
S
T
Q3  
2
Q4  
6
Q5  
7
Q6  
14  
8
CLR  
R
Q7  
9
Q8  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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具有 I2C 控制接口的 1 线路至 18 线路时钟驱动器 | DL | 48 | 0 t