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CDC319DBG4 PDF预览

CDC319DBG4

更新时间: 2024-11-18 15:45:43
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 364K
描述
1-Line to 10-Line Clock Driver with I<sup>2</sup>C Control Interface 28-SSOP 0 to 70

CDC319DBG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP28,.3
针数:28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.37
系列:319输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e4
长度:10.2 mm负载电容(CL):30 pF
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.006 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:10最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.5 mA
Prop。Delay @ Nom-Sup:150 ns传播延迟(tpd):3.6 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

CDC319DBG4 数据手册

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CDC319  
1-LINE TO 10-LINE CLOCK DRIVER  
2
WITH I C CONTROL INTERFACE  
SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001  
DB PACKAGE  
(TOP VIEW)  
High-Speed, Low-Skew 1-to-10 Clock Buffer  
for SDRAM (Synchronous DRAM) Clock  
Buffering Applications  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
1Y0  
V
CC  
CC  
Output Skew, t  
, Less Than 250 ps  
2
sk(o)  
2Y3  
2Y2  
GND  
3
1Y1  
GND  
Pulse Skew, t  
, Less Than 500 ps  
sk(p)  
4
Supports up to Two Unbuffered SDRAM  
DIMMs (Dual Inline Memory Modules)  
5
V
V
CC  
CC  
6
1Y2  
1Y3  
GND  
A
2Y1  
2Y0  
GND  
OE  
2
I C Serial Interface Provides Individual  
7
Enable Control for Each Output  
8
9
Operates at 3.3 V  
10  
11  
12  
13  
14  
V
V
CC  
CC  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
3Y0  
GND  
3Y1  
GND  
GND  
SCLOCK  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
V
CC  
SDATA  
Packaged in 28-Pin Shrink Small Outline  
(DB) Package  
description  
The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum  
skew for clock distribution. The CDC319 operates from a 3.3-V power supply, and is characterized for operation  
from 0°C to 70°C.  
2
The device provides a standard mode (100K-bits/s) I C serial interface for device control. The implementation  
2
2
is as a slave/receiver. The device address is specified in the I C device address table. Both of the I C inputs  
(SDATA and SCLOCK) provide integrated pullup resistors (typically 140 k) and are 5-V tolerant.  
2
Three 8-bit I C registers provide individual enable control for each of the outputs. All outputs default to enabled  
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit  
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,  
random access of the registers is not supported).  
The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a  
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.  
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CDC319DBG4 替代型号

型号 品牌 替代类型 描述 数据表
CDC319DBR TI

完全替代

1Line to 10Line Clock Driver
CDC319DB TI

完全替代

1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

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