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CDC319DB

更新时间： 2024-11-18 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
11页 170K
描述
1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

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中文翻译

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CDC319DB 数据手册

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CDC319  
1-LINE TO 10-LINE CLOCK DRIVER  
2
WITH I C CONTROL INTERFACE  
SCAS590 – DECEMBER 1997  
DB PACKAGE  
(TOP VIEW)  
High-Speed, Low-Skew 1-to-10 Clock Buffer  
for SDRAM (Synchronous DRAM) Clock  
Buffering Applications  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
1Y0  
1Y1  
GND  
V
1Y2  
1Y3  
GND  
A
V
CC  
CC  
Output Skew, t  
, Less Than 250 ps  
2
sk(o)  
2Y3  
2Y2  
GND  
3
Pulse Skew, t  
, Less Than 500 ps  
sk(p)  
4
Supports up to Two Unbuffered SDRAM  
DIMMs (Dual Inline Memory Modules)  
5
V
CC  
CC  
6
2Y1  
2Y0  
GND  
OE  
2
I C Serial Interface Provides Individual  
7
Enable Control for Each Output  
8
9
Operates at 3.3 V  
10  
11  
12  
13  
14  
V
3Y0  
GND  
V
V
CC  
CC  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
3Y1  
GND  
GND  
SCLOCK  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
CC  
SDATA  
Packaged in 28-Pin Shrink Small Outline  
(DB) Package  
description  
The CDC319 is a high-performance clock buffer that distributes one input (A) to 10 outputs (Y) with minimum  
skew for clock distribution. The CDC319 operates from a 3.3-V power supply, and is characterized for operation  
from 0°C to 70°C.  
2
The device provides a standard mode (100K-bits/s) I C serial interface for device control. The implementation  
2
2
is as a slave/receiver. The device address is specified in the I C device address table. Both of the I C inputs  
(SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant.  
2
Three 8-bit I C registers provide individual enable control for each of the outputs. All outputs default to enabled  
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit  
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,  
random access of the registers is not supported).  
The CDC319 provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a  
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.  
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Intel is a trademark of Intel Corporation  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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CDC319DB 替代型号

型号 品牌 替代类型 描述 数据表
CDC319DBR TI

完全替代

 1Line to 10Line Clock Driver
CDC319DBG4 TI

完全替代

 1-Line to 10-Line Clock Driver with I<sup>2</sup>C Control Interface 28-SSOP 0

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