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CDC318A

更新时间： 2024-09-15 22:39:55
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
12页 184K
描述
1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

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CDC318A 数据手册

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CDC318A  
1-LINE TO 18-LINE CLOCK DRIVER  
2
WITH I C CONTROL INTERFACE  
SCAS614 – SEPTEMBER 1998  
DL PACKAGE  
(TOP VIEW)  
High-Speed, Low-Skew 1-to-18 Clock Buffer  
for Synchronous DRAM (SDRAM) Clock  
Buffering Applications  
1
2
3
4
5
6
7
8
9
48  
47  
46  
NC  
NC  
NC  
NC  
Output Skew, t  
, Less Than 250 ps  
sk(o)  
Pulse Skew, t  
, Less Than 500 ps  
sk(p)  
V
V
CC  
CC  
Supports up to Four Unbuffered SDRAM  
Dual Inline Memory Modules (DIMMs)  
1Y0  
1Y1  
GND  
45 4Y3  
44 4Y2  
43 GND  
2
I C Serial Interface Provides Individual  
Enable Control for Each Output  
V
42  
V
CC  
CC  
1Y2  
1Y3  
41 4Y1  
40 4Y0  
39 GND  
38 OE  
Operates at 3.3 V  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
GND 10  
A
11  
12  
100-MHz Operation  
V
V
37  
36 3Y3  
CC  
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015  
2Y0 13  
2Y1  
GND  
3Y2  
GND  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Packaged in 48-Pin Shrink Small Outline  
(DL) Package  
V
V
CC  
CC  
2Y2  
2Y3  
GND  
3Y1  
3Y0  
GND  
description  
The CDC318A is a high-performance clock buffer  
designed to distribute high-speed clocks in PC  
applications. This device distributes one input (A)  
to 18 outputs (Y) with minimum skew for clock  
distribution. The CDC318A operates from a 3.3-V  
power supply. It is characterized for operation  
from 0°C to 70°C.  
V
V
CC  
CC  
5Y0  
GND  
5Y1  
GND  
GND  
SCLOCK  
V
CC  
SDATA  
NC – No internal connection  
This device has been designed with consideration  
foroptimizedEMIperformance. Dependingonthe  
application layout, damping resistors in series to  
the clock outputs (like proposed in the PC100  
specification) may not be needed in most cases.  
2
The device provides a standard mode (100K-bits/s) I C serial interface for device control. The implementation  
2
2
is as a slave/receiver. The device address is specified in the I C device address table. Both of the I C inputs  
(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ).  
2
Three 8-bit I C registers provide individual enable control for each of the outputs. All outputs default to enabled  
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit  
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,  
random access of the registers is not supported).  
The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a  
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.  
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Intel is a trademark of Intel Corporation  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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