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CDC2582

更新时间： 2024-11-19 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 驱动器输入元件时钟
页数 文件大小 规格书
10页 145K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

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CDC2582 数据手册

 浏览型号CDC2582的Datasheet PDF文件第2页浏览型号CDC2582的Datasheet PDF文件第3页浏览型号CDC2582的Datasheet PDF文件第4页浏览型号CDC2582的Datasheet PDF文件第5页浏览型号CDC2582的Datasheet PDF文件第6页浏览型号CDC2582的Datasheet PDF文件第7页 
CDC2582  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
WITH DIFFERENTIAL LVPECL CLOCK INPUTS  
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996  
Low Output Skew for Clock-Distribution  
and Clock-Generation Applications  
Application for Synchronous DRAMs  
Outputs Have Internal 26-Ω Series  
Resistors to Dampen Transmission-Line  
Effects  
Operates at 3.3-V V  
CC  
Distributes Differential LVPECL Clock  
Inputs to 12 TTL-Compatible Outputs  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Two Select Inputs Configure Up to Nine  
Outputs to Operate at One-Half or Double  
the Input Frequency  
Distributed V  
and Ground Pins Reduce  
CC  
Switching Noise  
No External RC Network Required  
Packaged in 52-Pin Quad Flatpack  
External Feedback Input (FBIN) Is Used to  
Synchronize the Outputs With the Clock  
Inputs  
PAH PACKAGE  
(TOP VIEW)  
52 51 50 49 48 47 46 45 44 43 42 41 40  
39  
GND  
1Y1  
V
4Y3  
GND  
V
4Y2  
GND  
V
4Y1  
GND  
GND  
V
3Y3  
GND  
1
CC  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
2
V
3
CC  
GND  
1Y2  
4
CC  
5
V
6
CC  
GND  
1Y3  
7
CC  
8
V
9
CC  
GND  
GND  
2Y1  
10  
11  
12  
13  
CC  
V
CC  
14 15 16 17 18 19 20 21 22 23 24 25 26  
description  
The CDC2582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to  
precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN,  
CLKIN)inputsignals. Itisspecifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz  
on outputs configured as half-frequency outputs. Each output has an internal 26-Ω series resistor that improves  
the signal integrity at the load. The CDC2582 operates at 3.3-V V  
.
CC  
The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN)  
signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization  
between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback is synchronized  
to the same frequency as the clock (CLKIN and CLKIN) inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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