CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS303
Maximum Output Skew Between Same
Phase Outputs of 1 ns
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q2
Q1
CLR
Q3
Q4
GND
GND
GND
Q5
Maximum Pulse Skew of 1 ns
TTL-Compatible Inputs and Outputs
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
V
CC
CC
V
CC
CLK
PRE
Q8
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
Q6
Q7
description
The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six
in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC303 has output and pulse-skew parameters t
when a divide-by-two function is required.
and t
to ensure performance as a clock driver
sk(o)
sk(p)
The CDC303 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
PRE
H
CLK Q1–Q6 Q7–Q8
X
X
X
↑
L
H
L
H
L
H
†
L
†
L
L
L
H
H
Q
Q
Q
Q
0
0
0
0
H
H
L
†
This configuration does not persist when
PRE or CLR returns to its inactive (high)
level.
‡
logic symbol
15
Q1
16
Q2
1
10
11
PRE
CLK
S
T
Q3
2
Q4
6
Q5
7
Q6
8
14
CLR
R
Q7
9
Q8
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265