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CDC2582PAH PDF预览

CDC2582PAH

更新时间： 2024-11-04 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路输入元件信息通信管理
页数 文件大小 规格书
10页 145K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

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中文翻译

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CDC2582PAH 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：TQFP, TQFP52,.47SQ
针数：52Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：8.59系列：CDC
输入调节：DIFFERENTIALJESD-30 代码：S-PQFP-G52
JESD-609代码：e4长度：10 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：4功能数量：1
反相输出次数：端子数量：52
实输出次数：12最高工作温度：70 °C
最低工作温度：输出特性：3-STATE WITH SERIES RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP52,.47SQ封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.5 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mm最小 fmax：100 MHz
Base Number Matches：1

CDC2582PAH 数据手册

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CDC2582  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
WITH DIFFERENTIAL LVPECL CLOCK INPUTS  
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996  
Low Output Skew for Clock-Distribution  
and Clock-Generation Applications  
Application for Synchronous DRAMs  
Outputs Have Internal 26-Ω Series  
Resistors to Dampen Transmission-Line  
Effects  
Operates at 3.3-V V  
CC  
Distributes Differential LVPECL Clock  
Inputs to 12 TTL-Compatible Outputs  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Two Select Inputs Configure Up to Nine  
Outputs to Operate at One-Half or Double  
the Input Frequency  
Distributed V  
and Ground Pins Reduce  
CC  
Switching Noise  
No External RC Network Required  
Packaged in 52-Pin Quad Flatpack  
External Feedback Input (FBIN) Is Used to  
Synchronize the Outputs With the Clock  
Inputs  
PAH PACKAGE  
(TOP VIEW)  
52 51 50 49 48 47 46 45 44 43 42 41 40  
39  
GND  
1Y1  
V
4Y3  
GND  
V
4Y2  
GND  
V
4Y1  
GND  
GND  
V
3Y3  
GND  
1
CC  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
2
V
3
CC  
GND  
1Y2  
4
CC  
5
V
6
CC  
GND  
1Y3  
7
CC  
8
V
9
CC  
GND  
GND  
2Y1  
10  
11  
12  
13  
CC  
V
CC  
14 15 16 17 18 19 20 21 22 23 24 25 26  
description  
The CDC2582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to  
precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN,  
CLKIN)inputsignals. Itisspecifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz  
on outputs configured as half-frequency outputs. Each output has an internal 26-Ω series resistor that improves  
the signal integrity at the load. The CDC2582 operates at 3.3-V V  
.
CC  
The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN)  
signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization  
between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback is synchronized  
to the same frequency as the clock (CLKIN and CLKIN) inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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