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CDC2586PAHR PDF预览

CDC2586PAHR

更新时间： 2024-11-20 13:06:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器输出元件
页数 文件大小 规格书
12页 167K
描述
3.3V PLL CLock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP

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中文翻译

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CDC2586PAHR 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP, TQFP52,.47SQ,25针数：52
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.78
系列：2586输入调节：STANDARD
JESD-30 代码：S-PQFP-G52JESD-609代码：e4
长度：10 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：4
功能数量：1反相输出次数：
端子数量：52实输出次数：12
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE WITH SERIES RESISTOR封装主体材料：PLASTIC/EPOXY
封装代码：TQFP封装等效代码：TQFP52,.47SQ,25
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.5 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
最小 fmax：100 MHzBase Number Matches：1

CDC2586PAHR 数据手册

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CDC2586  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998  
Low Output Skew for Clock-Distribution  
and Clock-Generation Applications  
Application for Synchronous DRAM,  
High-Speed Microprocessor  
Operates at 3.3-V V  
TTL-Compatible Inputs and Outputs  
CC  
Distributes One Clock Input to Twelve  
Outputs  
Outputs Have Internal 26-Ω Series  
Resistors to Dampen Transmission-Line  
Effects  
Two Select Inputs Configure Up to Nine  
Outputs to Operate at One-Half or Double  
the Input Frequency  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
No External RC Network Required  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
External Feedback (FBIN) Synchronizes the  
Outputs to the Clock Input  
Packaged in 52-Pin Thin Quad Flat Package  
PAH PACKAGE  
(TOP VIEW)  
52 51 50 49 48 47 46 45 44 43 42 41 40  
39  
GND  
1Y1  
V
4Y3  
GND  
V
4Y2  
GND  
V
4Y1  
GND  
GND  
V
3Y3  
GND  
1
CC  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
2
V
3
CC  
GND  
1Y2  
4
CC  
5
V
6
CC  
GND  
1Y3  
7
CC  
8
V
9
CC  
GND  
GND  
2Y1  
10  
11  
12  
13  
CC  
V
CC  
14 15 16 17 18 19 20 21 22 23 24 25 26  
NC – No internal connection  
description  
The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to  
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is  
specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or  
down to 25 MHz on outputs configured for half-frequency operation. Each output has an internal 26-Ω series  
resistor that improves the signal integrity at the load. The CDC2586 operates at nominal 3.3-V V  
.
CC  
The feedback input (FBIN) synchronizes the output clocks in frequency and phase to CLKIN. One of the twelve  
output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs.  
The output used as feedback is synchronized to the same frequency as CLKIN.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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CDC2586PAHR 替代型号

型号 品牌 替代类型 描述 数据表
CDC2586PAH TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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