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CDC2509BPWRG4 PDF预览

CDC2509BPWRG4

更新时间： 2024-09-13 12:36:19
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
14页 631K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDC2509BPWRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.73
Is Samacsys：N系列：2509
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
负载电容（CL）：30 pF逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：24实输出次数：9
最高工作温度：70 °C最低工作温度：
输出特性：SERIES-RESISTOR封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最小 fmax：125 MHz
Base Number Matches：1

CDC2509BPWRG4 数据手册

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SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004  
PW PACKAGE  
(TOP VIEW)  
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Use CDCVF2509A as a Replacement for  
this Device  
Designed to Meet PC SDRAM Registered  
DIMM Specification  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
2
CC  
CC  
Spread Spectrum Clock Compatible  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
Operating Frequency 25 MHz to 125 MHz  
2Y0  
2Y1  
GND  
GND  
2Y2  
2Y3  
4
5
Phase Error Time Minus Jitter at 66 MHz to  
100 MHz Is 150 ps  
6
7
Jitter (peak − peak) at 66 MHz to 100 MHz Is  
80 ps  
8
1Y4  
9
Jitter (cycle − cycle) at 66 MHz to 100 MHz  
Is |100 ps|  
V
10  
11  
12  
V
CC  
CC  
1G  
FBOUT  
2G  
FBIN  
D
Available in Plastic 24-Pin TSSOP  
D
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
D
D
D
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
Separate Output Enable for Each Output  
Bank  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
D
D
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On-Chip Series Damping Resstors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers. They use a PLL  
to precisely a, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
They are specifically designed for use with synchronous DRAMs. The CDC2509B operates at 3.3-V V . They  
CC  
also provide integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled  
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in  
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDC2509B does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2509B requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2001 − 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

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