Datasheet > CDC2510_15

CDC2510_15

更新时间： 2024-09-14 02:58:43

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
9页	133K
描述
3.3V Phase-Lock Loop Clock Driver

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CDC2510_15 数据手册

CDC2510

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS597 – DECEMBER 1997

PW PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Ten Outputs

AGND

CLK

Single Output Enable Terminal Controls All

Ten Outputs

1Y0

1Y1

1Y2

GND

1Y3

1Y9

1Y8

GND

1Y7

1Y6

External Feedback (FBIN) Pin Is Used to

Synchronize the Outputs to the Clock Input

On-Chip Series Damping Resistors

No External RC Network Required

1Y4

Operates at 3.3-V V

15 1Y5

Packaged in Plastic 24-Pin Thin Shrink

Small-Outline Package

FBOUT

FBIN

description

The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to

precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It

is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V V

integrated series-damping resistors that make it ideal for driving point-to-point loads.

and provides

One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output

enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input

is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

feedback signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDC2510 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

CLK

OUTPUTS

FBOUT

(0:9)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与CDC2510_15相关器件

型号	品牌	获取价格	描述	数据表
CDC2510A	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510APW	ETC	获取价格	TEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|TSSOP\|24PIN\|PLASTIC
CDC2510APWLE	ETC	获取价格	Ten Distributed-Output Clock Driver
CDC2510APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510APWRG4	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510B	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510B_15	TI	获取价格	3.3V Phase-Lock Loop Clock Driver
CDC2510BPW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWLE	ETC	获取价格	Ten Distributed-Output Clock Driver
CDC2510BPWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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