5秒后页面跳转
捷配首页

Datasheet > CDC2510BPWRG4
CDC2510BPWRG4 PDF预览

CDC2510BPWRG4

更新时间： 2024-11-17 14:06:59
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 638K
描述
3.3-V Phase-Lock Loop Clock Driver 24-TSSOP

阅读下载

中文翻译

获取价格

CDC2510BPWRG4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP24,.25
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.31
Is Samacsys：N系列：2510
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.012 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：24
实输出次数：10最高工作温度：70 °C
最低工作温度：输出特性：SERIES-RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
最小 fmax：125 MHzBase Number Matches：1

CDC2510BPWRG4 数据手册

 浏览型号CDC2510BPWRG4的Datasheet PDF文件第2页浏览型号CDC2510BPWRG4的Datasheet PDF文件第3页浏览型号CDC2510BPWRG4的Datasheet PDF文件第4页浏览型号CDC2510BPWRG4的Datasheet PDF文件第5页浏览型号CDC2510BPWRG4的Datasheet PDF文件第6页浏览型号CDC2510BPWRG4的Datasheet PDF文件第7页 
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ  
ꢇ ꢈꢇ ꢉꢊ ꢋꢌꢍ ꢎꢏꢉꢐ ꢑ ꢀꢒ ꢐ ꢑꢑ ꢋ ꢀꢐ ꢑ ꢀꢒ ꢁ ꢓꢔ ꢊ ꢏꢓ  
ꢕ
SCAS612 B− SEPTEMBER 1998 − REVISED DECEMBER 2004  
PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
Use CDCVF2510A as a Replacement for  
this Device  
Designed to Meet PC SDRAM Registered  
DIMM Specification  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
V
2
CC  
CC  
Spread Spectrum Clock Compatible  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
Operating Frequency 25 MHz to 125 MHz  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
4
5
tPhase Error Minus Jitter at 66 MHz to  
100 MHz Is 150 ps  
6
7
Jitter (pk − pk) at 66 MHz to 100 MHz is  
80ps  
8
1Y4  
9
Jitter (cyc − cyc) at 66 MHz to 100 MHz is  
|100 ps|  
V
10  
11  
12  
15 1Y5  
CC  
G
V
14  
13  
CC  
D
Available in Plastic 24-Pin TSSOP  
FBOUT  
FBIN  
D
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
D
D
D
Distributes One Clock Input to One Bank of  
Ten Outputs  
Separate Output Enable for Each Output  
Bank  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
D
D
D
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3-V  
description  
The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V V . It also  
CC  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted  
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output  
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input  
is low, the outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2510B requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢋ
ꢋ
ꢓ
ꢑ
ꢨ
ꢁ
ꢣ
ꢖ
ꢀ
ꢡ
ꢗ
ꢢ
ꢔ
ꢜ
ꢑ
ꢚ
ꢘ
ꢛ
ꢁ
ꢍ
ꢗ
ꢍ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢗꢤ  
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢈ
Copyright 2004, Texas Instruments Incorporated  
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢩ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢪ
ꢟ
ꢔ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢫ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢈ  
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢬ
ꢈ
ꢋ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢭ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢬ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

下载PDF

CDC2510BPWRG4 替代型号

型号 品牌 替代类型 描述 数据表
CDC2510BPWR TI

完全替代

 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDC2510BPWRG4相关器件

型号 品牌 获取价格 描述 数据表
CDC2510C TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510C_15 TI

获取价格

 		3.3V Phase- Lock Loop Clock Driver
CDC2510CPW TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510CPWG4 TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510CPWR TI

获取价格

 		TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TSSOP|24PIN|PLASTIC
CDC2510CPWRG4 TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510PW TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510PWLE ETC

获取价格

 		Ten Distributed-Output Clock Driver
CDC2510PWR TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510PWRG4 TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver 24-TSSOP

与CDC2510BPWRG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证