5秒后页面跳转
CDC2510CPWG4 PDF预览

CDC2510CPWG4

更新时间: 2024-11-05 15:29:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 694K
描述
3.3-V Phase-Lock Loop Clock Driver 24-TSSOP

CDC2510CPWG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP24,.25
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.24
系列:2510输入调节:STANDARD
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:7.8 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:10
最高工作温度:85 °C最低工作温度:
输出特性:SERIES-RESISTOR封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:OTHER端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最小 fmax:125 MHz
Base Number Matches:1

CDC2510CPWG4 数据手册

 浏览型号CDC2510CPWG4的Datasheet PDF文件第2页浏览型号CDC2510CPWG4的Datasheet PDF文件第3页浏览型号CDC2510CPWG4的Datasheet PDF文件第4页浏览型号CDC2510CPWG4的Datasheet PDF文件第5页浏览型号CDC2510CPWG4的Datasheet PDF文件第6页浏览型号CDC2510CPWG4的Datasheet PDF文件第7页 
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢀ  
ꢆ ꢇꢆ ꢈꢉ ꢊꢋꢌ ꢍꢎꢈꢏ ꢐ ꢀꢑ ꢏ ꢐꢐ ꢊ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢉ ꢎꢒ  
SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004  
PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
Use CDCVF2510A as a Replacement for  
this Device  
Designed to Meet PC SDRAM Registered  
DIMM Design Support Document Rev. 1.2  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
V
2
CC  
CC  
Spread Spectrum Clock Compatible  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
Operating Frequency 25 MHz to 125 MHz  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
4
5
Static tPhase Error Distribution at 66 MHz  
to 100 MHz is 150 ps  
6
7
Drop-In Replacement for TI CDC2510A With  
Enhanced Performance  
8
1Y4  
9
Jitter (cyc − cyc) at 66 MHz to 100 MHz is  
|100 ps|  
V
10  
11  
12  
15 1Y5  
CC  
G
V
14  
13  
CC  
D
Available in Plastic 24-Pin TSSOP  
FBOUT  
FBIN  
D
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
D
D
Distributes One Clock Input to One Bank of  
Ten Outputs  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
D
D
D
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at V  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
= 3.3 V . It also  
CC  
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted  
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output  
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input  
is low, the outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC2510C is characterized for operation from 0°C to 85°C.  
For application information, see the High Speed Distribution Design Techniques for  
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread  
Spectrum Clocking (SSC) (literature number SCAA039) application reports.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢖꢣ  
Copyright 2004, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢇ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CDC2510CPWG4 替代型号

型号 品牌 替代类型 描述 数据表
CDC2510CPWR TI

完全替代

TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TSSOP|24PIN|PLASTIC
CY2510ZXC-1 CYPRESS

功能相似

Spread Aware Ten/Eleven Output Zero Delay Buffer

与CDC2510CPWG4相关器件

型号 品牌 获取价格 描述 数据表
CDC2510CPWR TI

获取价格

TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|TSSOP|24PIN|PLASTIC
CDC2510CPWRG4 TI

获取价格

3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510PW TI

获取价格

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510PWLE ETC

获取价格

Ten Distributed-Output Clock Driver
CDC2510PWR TI

获取价格

3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510PWRG4 TI

获取价格

3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2516 TI

获取价格

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2516DGG TI

获取价格

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2516DGGR TI

获取价格

3.3V Phase- Lock Loop Clock Driver
CDC2536 TI

获取价格

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS