Datasheet > CDC2516DGG

CDC2516DGG

更新时间： 2024-11-04 22:40:11

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
11页	161K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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CDC2516DGG 数据手册

CDC2516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998

DGG PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to Four Banks

of Four Outputs

1Y0

1Y1

GND

1Y2

1Y3

4Y0

4Y1

GND

4Y2

4Y3

Separate Output Enable for Each Output

Bank

External Feedback Pin (FBIN) Is Used to

Synchronize the Outputs to the Clock Input

On-Chip Series-Damping Resistors

No External RC Network Required

Operates at 3.3-V V

GND 10

39 GND

Packaged in Plastic 48-Pin Thin Shrink

Small-Outline Package

CLK

FBIN

AGND 13

AGND 14

GND 15

2G 16

36 AGND

35 FBOUT

34 GND

33 3G

description

The CDC2516 is a high-performance, low-skew,

low-jitter, phase-lock loop (PLL) clock driver. It

uses a PLL to precisely align, in both frequency

and phase, the feedback output (FBOUT) to the

clock (CLK) input signal. It is specifically designed

for use with synchronous DRAMs. The CDC2516

operates at 3.3-V V

series-damping resistors that make it ideal for

driving point-to-point loads.

2Y0 18

2Y1 19

GND 20

GND 21

2Y2 22

2Y3 23

31 3Y0

30 3Y1

29 GND

28 GND

27 3Y2

26 3Y3

and provides integrated

Four banks of four outputs provide 16 low-skew,

low-jitter copies of the input clock. Output signal

duty cycles are adjusted to 50 percent,

independent of the duty cycle at the input clock.

Each bank of outputs can be enabled or disabled

separately via the 1G, 2G, 3G, and 4G control

inputs. When the G inputs are high, the outputs

switchinphaseandfrequencywithCLK;whenthe

G inputs are low, the outputs are disabled to the

logic-low state.

Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

feedback signals. The PLL may be bypassed for test purposes by strapping AV

to ground.

The CDC2516 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与CDC2516DGG相关器件

型号	品牌	获取价格	描述	数据表
CDC2516DGGR	TI	获取价格	3.3V Phase- Lock Loop Clock Driver
CDC2536	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC2536DB	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC2536DBLE	TI	获取价格	CDC SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28, PLASTI
CDC2536DBR	TI	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER
CDC2536DLR	TI	获取价格	3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC2582	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
CDC2582PAH	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
CDC2582PBG	ETC	获取价格	Twelve Distributed-Output Clock Driver
CDC2586	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

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