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CDC2510A PDF预览

CDC2510A

更新时间： 2024-09-13 04:11:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
13页 308K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDC2510A 数据手册

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SCAS604C− APRIL 1998 − REVISED DECEMBER 2004  
PW PACKAGE  
(TOP VIEW)  
D
Use CDCVF2510A as a Replacement for  
this Device  
D
D
D
D
D
D
D
Spread Spectrum Clock Compatible  
100-MHz Maximum Frequency  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
V
2
CC  
CC  
Available in Plastic 24-Pin TSSOP  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
1Y9  
1Y8  
GND  
GND  
1Y7  
1Y6  
4
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
5
6
Distributes One Clock Input to One Bank of  
Ten Outputs  
7
8
Single Output Enable Terminal Controls All  
Ten Outputs  
1Y4  
9
V
10  
11  
12  
15 1Y5  
CC  
G
External Feedback (FBIN) Pin Is Used to  
Synchronize the Outputs to the Clock Input  
V
14  
13  
CC  
FBOUT  
FBIN  
D
D
D
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3-V V  
CC  
description  
The CDC2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDC2510A operates at 3.3-V V  
integrated series-damping resistors that make it ideal for driving point-to-point loads.  
and provides  
CC  
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted  
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output  
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input  
is low, the outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDC2510A does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2510A requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC2510A is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
CLK  
OUTPUTS  
1Y  
G
FBOUT  
(0:9)  
X
L
L
L
L
L
H
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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