Datasheet > CDC2510APW

CDC2510APW

更新时间： 2024-11-18 23:41:35

品牌	Logo	应用领域
其他 - ETC		时钟驱动器光电二极管输出元件
页数	文件大小	规格书
9页	126K
描述
TEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|TSSOP\|24PIN\|PLASTIC

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CDC2510APW 数据手册

CDC2510A

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS604B– APRIL 1998 – REVISED JULY 2001

PW PACKAGE

(TOP VIEW)

Spread Spectrum Clock Compatible

100-MHz Maximum Frequency

Available in Plastic 24-Pin TSSOP

AGND

CLK

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

1Y0

1Y1

1Y2

GND

1Y3

1Y9

1Y8

GND

1Y7

1Y6

Distributes One Clock Input to One Bank of

Ten Outputs

Single Output Enable Terminal Controls All

Ten Outputs

External Feedback (FBIN) Pin Is Used to

Synchronize the Outputs to the Clock Input

1Y4

15 1Y5

On-Chip Series Damping Resistors

No External RC Network Required

FBOUT

FBIN

Operates at 3.3-V V

description

The CDC2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

ItisspecificallydesignedforusewithsynchronousDRAMs.TheCDC2510Aoperatesat3.3-VV andprovides

integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output

enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input

is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510A does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510A requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDC2510A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

CLK

OUTPUTS

FBOUT

(0:9)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与CDC2510APW相关器件

型号	品牌	获取价格	描述	数据表
CDC2510APWLE	ETC	获取价格	Ten Distributed-Output Clock Driver
CDC2510APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510APWRG4	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510B	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510B_15	TI	获取价格	3.3V Phase-Lock Loop Clock Driver
CDC2510BPW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWLE	ETC	获取价格	Ten Distributed-Output Clock Driver
CDC2510BPWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510C	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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