Datasheet > CDC2510B_15

CDC2510B_15

更新时间： 2024-11-06 02:58:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
10页	148K
描述
3.3V Phase-Lock Loop Clock Driver

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CDC2510B_15 数据手册

CDC2510B

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS612 – SEPTEMBER 1998

PW PACKAGE

(TOP VIEW)

Designed to Meet PC SDRAM Registered

DIMM Specification

Spread Spectrum Clock Compatible

AGND

CLK

Operating Frequency 25 MHz to 125 MHz

tPhase Error Minus Jitter at 66MHz to

100MHz is ±150ps

1Y0

1Y1

1Y2

GND

1Y3

1Y9

1Y8

GND

1Y7

1Y6

Jitter (pk – pk) at 66 MHz to 100 MHz is

±80ps

Jitter (cyc – cyc) at 66 MHz to 100 MHz is

|100 ps|

1Y4

Available in Plastic 24-Pin TSSOP

15 1Y5

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

FBOUT

FBIN

Distributes One Clock Input to One Bank of

Ten Outputs

Separate Output Enable for Each Output

Bank

External Feedback (FBIN) Terminal Is Used

to Synchronize the Outputs to the Clock

Input

On-Chip Series Damping Resistors

No External RC Network Required

Operates at 3.3-V

description

The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL

to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V V . It also

provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output

enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input

is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510B requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback

signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDC2510B is characterized for operation from 0°C to 70°C.

For application information refer to application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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与CDC2510B_15相关器件

型号	品牌	获取价格	描述	数据表
CDC2510BPW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWLE	ETC	获取价格	Ten Distributed-Output Clock Driver
CDC2510BPWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510BPWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510C	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510C_15	TI	获取价格	3.3V Phase- Lock Loop Clock Driver
CDC2510CPW	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510CPWG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP
CDC2510CPWR	TI	获取价格	TEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|TSSOP\|24PIN\|PLASTIC
CDC2510CPWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver 24-TSSOP

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