CDC2509PW

更新时间： 2024-11-29 22:28:27

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
9页	134K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CDC2509PW 数据手册

CDC2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS580A – OCTOBER 1996 – REVISED JANUARY 1998

PW PACKAGE

(TOP VIEW)

Phase-Lock Loop Clock Distribution for

Synchronous DRAM Applications

Distributes One Clock Input to One Bank of

Five and One Bank of Four Outputs

AGND

CLK

Separate Output Enable for Each Output

Bank

1Y0

1Y1

1Y2

GND

1Y3

2Y0

2Y1

GND

2Y2

2Y3

External Feedback (FBIN) Pin Is Used to

Synchronize the Outputs to the Clock Input

On-Chip Series Damping Resistors

No External RC Network Required

1Y4

Operates at 3.3-V V

Packaged in Plastic 24-Pin Thin Shrink

Small-Outline Package

FBOUT

FBIN

description

The CDC2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to

precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It

is specifically designed for use with synchronous DRAMs. The CDC2509 operates at 3.3-V V

integrated series-damping resistors that make it ideal for driving point-to-point loads.

and provides

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can

be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs

switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low

state.

Unlike many products containing PLLs, the CDC2509 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2509 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application

of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or

feedback signals. The PLL can be bypassed for test purposes by strapping AV

to ground.

The CDC2509 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

(0:4)

CLK

FBOUT

(0:3)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

中文翻译

下载PDF

与CDC2509PW相关器件

型号	品牌	获取价格	描述	数据表
CDC2509PWLE	ETC	获取价格	Nine Distributed-Output Clock Driver
CDC2509PWR	TI	获取价格	3-3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509PWRG4	TI	获取价格	3.3-V Phase-Lock Loop Clock Driver With 3-State Outputs 24-TSSOP
CDC2510	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510_15	TI	获取价格	3.3V Phase-Lock Loop Clock Driver
CDC2510A	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510APW	ETC	获取价格	TEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|TSSOP\|24PIN\|PLASTIC
CDC2510APWLE	ETC	获取价格	Ten Distributed-Output Clock Driver
CDC2510APWR	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2510APWRG4	TI	获取价格	3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDC2509PW相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

52
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

41
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

69
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

65

产品中心

服务支持

精选活动

关于我们

帮助中心

CDC2509PW

CDC2509PW 数据手册

与CDC2509PW相关器件

与CDC2509PW相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDC2509PW

CDC2509PW 数据手册

与CDC2509PW相关器件

与CDC2509PW相关文章

您还可以找

您在本页遇到什么问题？