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CDC2509CPWR PDF预览

CDC2509CPWR

更新时间： 2024-11-18 02:58:47
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 182K
描述
3.3V PHASE-LOCK LOOP CLOCK DRIVER

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中文翻译

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CDC2509CPWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.65
Is Samacsys：N系列：2509
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
负载电容（CL）：30 pF逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：24实输出次数：9
最高工作温度：85 °C最低工作温度：
输出特性：SERIES-RESISTOR封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.2 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：OTHER端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm最小 fmax：125 MHz
Base Number Matches：1

CDC2509CPWR 数据手册

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CDC2509C  
3.3-V PHASE-LOCK LOOP CLOCK DRIVER  
SCAS620 – DECEMBER 1998  
PW PACKAGE  
(TOP VIEW)  
Designed to Meet PC SDRAM Registered  
DIMM Design Support Document Rev. 1.2  
Spread Spectrum Clock Compatible  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Operating Frequency 25 MHz to 125 MHz  
V
2
CC  
CC  
Static tPhase Error Distribution at 66MHz to  
100 MHz is ±150 ps  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
2Y0  
2Y1  
GND  
GND  
2Y2  
2Y3  
4
5
Drop-In Replacement for TI CDC2509A With  
Enhanced Performance  
6
7
Jitter (cyc – cyc) at 66 MHz to 100 MHz is  
|100 ps|  
8
1Y4  
9
Available in Plastic 24-Pin TSSOP  
V
10  
11  
12  
V
CC  
CC  
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
1G  
FBOUT  
2G  
FBIN  
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
Separate Output Enable for Each Output  
Bank  
External Feedback (FBIN) Terminal Is Used  
to Synchronize the Outputs to the Clock  
Input  
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3 V  
description  
The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V V . It also  
CC  
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled  
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in  
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.  
Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter  
for the PLL is included on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC2509C is characterized for operation from 0°C to 85°C.  
For application information refer to application reports High Speed Distribution Design Techniques for  
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread  
Spectrum Clocking (SSC) (literature number SCAA039).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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CDC2509CPWR 替代型号

型号 品牌 替代类型 描述 数据表
CDCVF2509PW TI

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