生命周期: | Transferred | 包装说明: | TSSOP, |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.67 | 系列: | LV/LV-A/LVX/H |
JESD-30 代码: | R-PDSO-G16 | 长度: | 5 mm |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | J-K FLIP-FLOP |
位数: | 2 | 功能数量: | 2 |
端子数量: | 16 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 输出极性: | COMPLEMENTARY |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | TSSOP |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
传播延迟(tpd): | 16.5 ns | 认证状态: | Not Qualified |
座面最大高度: | 1.1 mm | 最大供电电压 (Vsup): | 3.6 V |
最小供电电压 (Vsup): | 2 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子形式: | GULL WING |
端子节距: | 0.65 mm | 端子位置: | DUAL |
触发器类型: | NEGATIVE EDGE | 宽度: | 4.4 mm |
最小 fmax: | 80 MHz | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74LVX112MX | TI |
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LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PD | |
74LVX112SJ | FAIRCHILD |
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Low Voltage Dual J-K Flip-Flops with Preset and Clear | |
74LVX112SJX | TI |
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LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PD | |
74LVX125 | FAIRCHILD |
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Low Voltage Quad Buffer with 3-STATE Outputs | |
74LVX125 | STMICROELECTRONICS |
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LOW VOLTAGE QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS | |
74LVX125_08 | FAIRCHILD |
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Low Voltage Quad Buffer with 3-STATE Outputs | |
74LVX125M | FAIRCHILD |
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Low Voltage Quad Buffer with 3-STATE Outputs | |
74LVX125M | ONSEMI |
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带 3 态输出的低压四路缓冲器 | |
74LVX125M_08 | FAIRCHILD |
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Low Voltage Quad Buffer with 3-STATE Outputs | |
74LVX125M_NL | FAIRCHILD |
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Bus Driver, LV/LV-A/LVX/H Series, 4-Func, 1-Bit, True Output, CMOS, PDSO14, 0.150 INCH, LE |