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74LVX125 PDF预览

74LVX125

更新时间: 2024-11-10 22:15:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
12页 231K
描述
LOW VOLTAGE QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS

74LVX125 数据手册

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74LVX125  
LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)  
WITH 5V TOLERANT INPUTS  
HIGH SPEED: t =4.4ns (TYP.) at V = 3.3V  
PD CC  
5V TOLERANT INPUTS  
POWER-DOWN PROTECTION ON INPUTS  
INPUT VOLTAGE LEVEL:  
V
= 0.8V, V = 2V at V =3V  
IL  
IH CC  
SOP  
TSSOP  
LOW POWER DISSIPATION:  
= 2 µA (MAX.) at T =25°C  
I
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V =3.3V  
Table 1: Order Codes  
PACKAGE  
V
OLP  
CC  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4 mA (MIN) at V =3V  
SOP  
74LVX125MTR  
74LVX125TTR  
OH  
OL  
CC  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
This device requires the 3-STATE control input G  
to be set high to place the output into the high  
impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V. It combines high speed  
performance with the true CMOS low power  
consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
V
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 125  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVX125 is a low voltage CMOS QUAD  
BUS BUFFERs fabricated with sub-micron silicon  
gate and double-layer metal wiring C MOS  
technology. It is ideal for low power, battery  
operated and low noise 3.3V applications.  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 3  
1/12  
August 2004  

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