Datasheet > 74LVX125T

74LVX125T

更新时间： 2024-01-18 18:24:41

品牌	Logo	应用领域
其他 - ETC		驱动器
页数	文件大小	规格书
9页	66K
描述
4-Bit Buffer/Driver

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中文翻译

获取价格

数据手册

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74LVX125T 数据手册

74LVX125

LOW VOLTAGE QUAD BUS BUFFERS (3-STATE)

WITH 5V TOLERANT INPUTS

■

HIGH SPEED:t_PD=4.4ns (TYP.) atV_CC= 3.3V

5V TOLERANT INPUTS

POWER-DOWN PROTECTIONON INPUTS

INPUT VOLTAGELEVEL:

V_IL=0.8V,V_IH=2V atV_CC=3V

LOW POWER DISSIPATION:

(Micro Package)

(TSSOPPackage)

■

I_CC=2 A (MAX.) at T_A=25 C

ORDER CODES :

LOWNOISE:

74LVX125M

74LVX125T

V_OLP=0.3 V (TYP.)at V_CC= 3.3V

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 4 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

This device requires the 3-STATE control input G

to be set high to place the output into the high

impedance state.

It has better speed performance at 3.3V than 5V

LS-TTL family combined with the true CMOS low

power consumption.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface5V to 3V.

OPERATING VOLTAGERANGE:

V_CC(OPR)= 2V to 3.6V(1.2VDataRetention)

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES125

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The LVX125 is a low voltage CMOS QUAD BUS

BUFFERS fabricated with sub-micron silicon gate

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

and

double-layer metal

wiring

C²MOS

technology.It is ideal for low power and low noise

3.3V applications.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/9

April 1999

12 3 4 5 6 7...9

中文翻译

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74LVX125TTR	STMICROELECTRONICS	获取价格	LOW VOLTAGE QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS
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