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74LVX132 PDF预览

74LVX132

更新时间: 2024-11-10 22:53:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
6页 91K
描述
Low Voltage Quad 2-Input NAND Schmitt Trigger

74LVX132 数据手册

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October 1996  
Revised February 2005  
74LVX132  
Low Voltage Quad 2-Input NAND Schmitt Trigger  
General Description  
Features  
The LVX132 contains four 2-input NAND Schmitt Trigger  
Gates. The pin configuration and function are the same as  
the LVX00 but the inputs have hysteresis between the pos-  
itive-going and negative-going input thresholds, which are  
capable of transforming slowly changing input signals into  
sharply defined, jitter-free output signals, thus providing  
greater noise margins than conventional gates.  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
The inputs tolerate voltages up to 7V allowing the interface  
of 5V systems to 3V systems.  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVX132M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX132SJ  
74LVX132MTC  
MTC14  
MTC14  
74LVX132MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Diagram  
Connection Diagram  
Pin Descriptions  
Pin Names  
An, Bn  
Yn  
Descriptions  
Inputs  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS012159  
www.fairchildsemi.com  

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