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74LVX132M PDF预览

74LVX132M

更新时间: 2024-01-26 19:21:36
品牌 Logo 应用领域
美国国家半导体 - NSC 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 121K
描述
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, PDSO14, 0.150 INCH, PLASTIC, SOIC-14, Gate

74LVX132M 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.150 INCH, PLASTIC, SOIC-14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.14
Is Samacsys:N系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3 VProp。Delay @ Nom-Sup:17.5 ns
传播延迟(tpd):17.5 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

74LVX132M 数据手册

 浏览型号74LVX132M的Datasheet PDF文件第2页浏览型号74LVX132M的Datasheet PDF文件第3页浏览型号74LVX132M的Datasheet PDF文件第4页浏览型号74LVX132M的Datasheet PDF文件第5页浏览型号74LVX132M的Datasheet PDF文件第6页 
December 1996  
74LVX132  
Low Voltage Quad 2-Input NAND Schmitt Trigger  
General Description  
Features  
Y
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Available in SOIC JEDEC, SOIC EIAJ and TSSOP  
packages  
The LVX132 contains four 2-input NAND Schmitt Trigger  
Gates. The pin configuration and function are the same as  
the LVX00 but the inputs have hysteresis between the posi-  
tive-going and negative-going input thresholds, which are  
capable of transforming slowly changing input signals into  
sharply defined, jitter-free output signals, thus providing  
greater noise margins than conventional gates.  
Y
Y
Y
Guaranteed simultaneous switching noise level and dy-  
namic threshold performance  
The inputs tolerate voltages up to 7V allowing the interface  
of 5V systems to 3V systems.  
SOIC JEDEC  
74LVX132M  
SOIC EIAJ  
TSSOP  
Order Number  
74LVX132SJ  
74LVX132MTC  
74LVX132MX 74LVX132SJX 74LVX132MTCX  
See NS Package Number  
M14A  
M14D  
MTC14  
Connection Diagram  
Logic Diagram  
Pin Assignment for  
TSSOP and SOIC  
TL/F/12159–2  
TL/F/12159–1  
C
1996 National Semiconductor Corporation  
TL/F/12159  
RRD-B30M17/Printed in U. S. A.  
http://www.national.com  

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