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74LVX132

更新时间： 2024-02-03 11:39:37

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
11页	230K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE WITH 5V TOLERANT INPUTS

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中文翻译

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74LVX132 数据手册

74LVX132

LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE

WITH 5V TOLERANT INPUTS

■

HIGH SPEED:

= 5.9ns (TYP.) at V = 3.3V

■

5V TOLERANT INPUTS

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

■

TYPICAL HYSTERESIS: 0.7V at V = 3.3V

LOW NOISE:

SOP

TSSOP

= 0.3V (TYP.) at V = 3.3V

OLP

■

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4mA (MIN)

BALANCED PROPAGATION DELAYS:

Table 1: Order Codes

PACKAGE

T & R

PLH

PHL

SOP

74LVX132MTR

74LVX132TTR

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

TSSOP

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 132

IMPROVED LATCH-UP IMMUNITY

POWER DOWN PROTECTION ON INPUTS

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

Pin configuration and function are the same as

those of the 74LVX00 but the 74LVX132 has

hysteresis.

This together with its schmitt trigger function

allows it to be used on line receivers with slow

rise/fall input signals.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

■

DESCRIPTION

The 74LVX132 is a low voltage CMOS QUAD

2-INPUT SCHMITT NAND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology. It is ideal for low

power, battery operated and low noise 3.3V

applications. Power down protection is provided

on all inputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 3

1/11

August 2004

12 3 4 5 6 7...11

中文翻译

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