74LVX126TTR

更新时间： 2024-11-10 22:34:31

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
9页	155K
描述
LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS

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替代型号

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74LVX126TTR 数据手册

74LVX126

LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE)

WITH 5V TOLERANT INPUTS

■

HIGH SPEED:

=4.4ns (TYP.) at V = 3.3V

■

5V TOLERANT INPUTS

POWER-DOWN PROTECTION ON INPUTS

INPUT VOLTAGE LEVEL:

= 0.8V, V = 2V at V =3V

IH CC

SOP

TSSOP

■

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

LOW NOISE:

= 0.3V (TYP.) at V =3.3V

ORDER CODES

PACKAGE

OLP

TUBE

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4 mA (MIN) at V =3V

SOP

74LVX126M

74LVX126MTR

74LVX126TTR

TSSOP

BALANCED PROPAGATION DELAYS:

PLH

PHL

This device requires the 3-STATE control input G

to be set low to place the output go in to the high

impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V. It combines high speed

performance with the true CMOS low power

consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 126

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVX126 is a low voltage CMOS QUAD

BUS BUFFERs fabricated with sub-micron silicon

gate and double-layer metal wiring C MOS

technology. It is ideal for low power, battery

operated and low noise 3.3V applications.

PIN CONNECTION AND IEC LOGIC SYMBOLS

July 2001

1/9

12 3 4 5 6 7...9

中文翻译

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74LVX126TTR 替代型号

型号	品牌	替代类型	描述	数据表
SN74LV126APWRG4	TI	功能相似	QUADRUPLE BUS BUFFER GATES WITH 3 STATE OUTPUTS

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