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74LVX125MT PDF预览

74LVX125MT

更新时间: 2024-11-10 22:15:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 90K
描述
Low Voltage Quad Buffer with 3-STATE Outputs

74LVX125MT 数据手册

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February 1994  
Revised February 2005  
74LVX125  
Low Voltage Quad Buffer with 3-STATE Outputs  
General Description  
The LVX125 contains four independent non-inverting buff-  
ers with 3-STATE outputs. The inputs tolerate voltages up  
to 7V allowing the interface of 5V systems to 3V systems.  
Features  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVX125M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX125SJ  
74LVX125MTC  
MTC14  
MTC14  
74LVX125MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
Inputs  
Output  
On  
Pin Descriptions  
OEn  
An  
Pin Names  
Description  
Inputs  
L
L
L
H
X
L
H
Z
An  
OEn  
On  
Output Enable Inputs  
Outputs  
H
H
L
Z
X
HIGH Voltage Level  
LOW Voltage Level  
High Impedance  
Immaterial  
© 2005 Fairchild Semiconductor Corporation  
DS012007  
www.fairchildsemi.com  

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