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74LVX125SJX PDF预览

74LVX125SJX

更新时间: 2024-01-13 16:42:16
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 310K
描述
Low Voltage Quad Buffer with 3-STATE Outputs

74LVX125SJX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOP
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.68
Is Samacsys:N控制类型:ENABLE LOW
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:12 ns传播延迟(tpd):17 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74LVX125SJX 数据手册

 浏览型号74LVX125SJX的Datasheet PDF文件第2页浏览型号74LVX125SJX的Datasheet PDF文件第3页浏览型号74LVX125SJX的Datasheet PDF文件第4页浏览型号74LVX125SJX的Datasheet PDF文件第5页浏览型号74LVX125SJX的Datasheet PDF文件第6页浏览型号74LVX125SJX的Datasheet PDF文件第7页 
February 2008  
74LVX125  
Low Voltage Quad Buffer with 3-STATE Outputs  
Features  
General Description  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
The LVX125 contains four independent non-inverting  
buffers with 3-STATE outputs. The inputs tolerate volt-  
ages up to 7V allowing the interface of 5V systems to 3V  
systems.  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Information  
Order  
Number  
Package  
Number  
Package Description  
74LVX125M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX125SJ  
74LVX125MTC  
MTC14  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
All packages are lead free per JEDEC: J-STD-020B standard.  
Connection Diagram  
Logic Symbol  
IEEE/IEC  
Pin Description  
Truth Table  
Pin Names  
Description  
Inputs  
Output  
A
Inputs  
n
OE  
L
A
O
n
n
n
OE  
Output Enable Inputs  
Outputs  
L
L
H
Z
n
O
L
H
X
n
H
H = HIGH Voltage Level  
L = LOW Voltage Level  
Z = High Impedance  
X = Immaterial  
©1994 Fairchild Semiconductor Corporation  
74LVX125 Rev. 1.4.0  
www.fairchildsemi.com  

74LVX125SJX 替代型号

型号 品牌 替代类型 描述 数据表
74LVX125SJ FAIRCHILD

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Low Voltage Quad Buffer with 3-STATE Outputs
SN74LV125ATD TI

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