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UPA2352T1G-E4-A PDF预览

UPA2352T1G-E4-A

更新时间： 2024-09-15 15:56:03
品牌 Logo 应用领域
日电电子 - NEC ISM频段晶体管
页数 文件大小 规格书
9页 319K
描述
Small Signal Field-Effect Transistor, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, EFLIP PACKAGE, 4 PIN

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UPA2352T1G-E4-A 技术参数

是否Rohs认证：符合生命周期：Transferred
包装说明：LEAD FREE, EFLIP PACKAGE, 4 PINReach Compliance Code：compliant
风险等级：5.7Is Samacsys：N
配置：COMMON DRAIN, 2 ELEMENTS WITH BUILT-IN DIODEFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：S-PBGA-X4JESD-609代码：e6
元件数量：2端子数量：4
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：260极性/信道类型：N-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子面层：TIN BISMUTH端子形式：UNSPECIFIED
端子位置：BOTTOM处于峰值回流温度下的最长时间：10
晶体管元件材料：SILICONBase Number Matches：1

UPA2352T1G-E4-A 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
μPA2352  
Dual N-CHANNEL MOSFET  
DESCRIPTION  
OUTLINE DRAWING (Unit: mm)  
The μPA2352 is a Dual N-channel MOSFET designed for Lithium-  
Ion battery protection circuit.  
TOP VIEW  
1.40 0.02  
BOTTOM VIEW  
0.65  
Ecologically Flip chip MOSFET for Lithium-Ion battery Protection  
(EFLIP).  
FEATURES  
G2  
G1  
S2  
S1  
•
Monolithic Dual MOSFET  
0.65  
Connecting the Drains on the circuit board is not required  
because the Drains of the FET1 and the FET2 are internally  
connected.  
•
2.5 V drive available and low on-state resistance  
RSS(on)1 = 43.0 mΩ MAX. (VGS = 4.5 V, IS = 2.0 A)  
RSS(on)2 = 45.0 mΩ MAX. (VGS = 4.0 V, IS = 2.0 A)  
RSS(on)3 = 55.0 mΩ MAX. (VGS = 3.1 V, IS = 2.0 A)  
RSS(on)4 = 67.0 mΩ MAX. (VGS = 2.5 V, IS = 2.0 A)  
Built-in G-S protection diode against ESD  
Pb-free bump  
Dot area (For in-house)  
// 0.1  
1-pin index mark S1  
4 - φ 0.37  
S
S1 : Source1  
G1 : Gate1  
G2 : Gate2  
S2 : Source2  
0.2 0.02  
S
0.28 0.03  
•
•
0.08 S  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
μPA2352T1G-E4-A Note  
4 PIN EFLIP  
EQUIVALENT CIRCUIT  
Note "-A" indicates Pb-free (This product does not contain Pb in  
external electrode and other parts)."-E4" indicates the unit  
orientation (-E4 only).  
FET2  
FET1  
Gate2  
Gate1  
Gate  
Protection  
Diode  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Source to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VSS = 0 V)  
Source Current (DC) Note1  
Source Current (pulse) Note2  
Total Power Dissipation (2units) Note1  
Channel Temperature  
VSSS  
VGSS  
IS(DC)  
IS(pulse)  
PT  
24  
±12  
V
V
±4.0  
A
Source2  
Source1  
±40  
A
Body Diode  
0.75  
W
°C  
°C  
Tch  
150  
Storage Temperature  
Tstg  
−55 to +150  
Notes 1. Mounted on BT resin board of 40.5 mm x 25 mm x 1.5 mm  
2. PW ≤ 100 μs, Duty Cycle ≤ 1%  
<R>  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this  
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage  
may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No.  
Date Published October 2006 NS CP(K)  
Printed in Japan  
G17881EJ2V0DS00 (2nd edition)  
2006  
The mark <R> shows major revised points.  
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.  
1234567...9

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