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UPA2350BT1G-E4-A PDF预览

UPA2350BT1G-E4-A

更新时间： 2024-09-15 21:15:03
品牌 Logo 应用领域
日电电子 - NEC ISM频段开关晶体管
页数 文件大小 规格书
7页 266K
描述
Power Field-Effect Transistor, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, EFLIP, 4 PIN

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UPA2350BT1G-E4-A 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：FLIP-CHIP包装说明：GRID ARRAY, S-XBGA-B4
针数：4Reach Compliance Code：compliant
风险等级：5.33配置：COMPLEX
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：S-XBGA-B4
JESD-609代码：e6元件数量：2
端子数量：4工作模式：ENHANCEMENT MODE
封装主体材料：UNSPECIFIED封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL认证状态：Not Qualified
表面贴装：YES端子面层：TIN BISMUTH
端子形式：BALL端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

UPA2350BT1G-E4-A 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
μPA2350B  
DUAL N-CHANNEL MOSFET  
FOR SWITCHING  
OUTLINE DRAWING (Unit: mm)  
DESCRIPTION  
The μ PA2350B is a Dual N-channel MOSFET designed for  
Lithium-Ion battery protection circuit.  
TOP VIEW  
1.47 0.02  
BOTTOM VIEW  
0.65  
Ecologically Flip chip MOSFET for Lithium-Ion battery Protection  
(EFLIP).  
G2  
G1  
S2  
S1  
FEATURES  
•
Monolithic Dual MOSFET  
0.65  
Connecting the Drains on the circuit board is not required  
because the Drains of the FET1 and the FET2 are internally  
connected.  
•
2.5 V drive available and low on-state resistance  
RSS(on)1 = 35 mΩ MAX. (VGS = 4.5 V, IS = 3.0 A)  
RSS(on)2 = 37 mΩ MAX. (VGS = 4.0 V, IS = 3.0 A)  
RSS(on)3 = 44 mΩ MAX. (VGS = 3.1 V, IS = 3.0 A)  
RSS(on)4 = 55 mΩ MAX. (VGS = 2.5 V, IS = 3.0 A)  
Built-in G-S protection diode against ESD  
Pb-free Bump  
Dot area (For in-house)  
// 0.1  
1-pin index mark S1  
φ
4 - 0.37  
S
S1: Source 1  
G1: Gate 1  
G2: Gate 2  
S2: Source 2  
0.2 0.02  
S
0.28 0.03  
•
•
0.08 S  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
4-pin EFLIP  
Note  
μ PA2350BT1G-E4-A  
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)  
EQUIVALENT CIRCUIT  
Remark "-E4" indicates the unit orientation (E4 only).  
FET2  
FET1  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Source to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VSS = 0 V)  
Source Current (DC) Note1  
Source Current (pulse) Note2  
Total Power Dissipation Note1  
Channel Temperature  
VSSS  
VGSS  
IS(DC)  
IS(pulse)  
PT  
20  
V
V
Gate 1  
Gate 2  
12  
6.0  
Gate  
Protection  
Diode  
A
50  
A
1.3  
W
°C  
°C  
Tch  
150  
Storage Temperature  
Tstg  
−55 to +150  
Source 1  
Source 2  
Notes 1. Mounted on ceramic board of 50 cm2 x 1.0 mmt  
2. PW ≤ 100 μs, Single Pulse  
Body Diode  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this  
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage  
may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G19313EJ1V0DS00 (1st edition)  
Date Published June 2008 NS  
Printed in Japan  
2008  
1234567

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