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SY100E431JI-TR PDF预览

SY100E431JI-TR

更新时间: 2024-11-21 05:53:27
品牌 Logo 应用领域
美国微芯 - MICROCHIP 输出元件逻辑集成电路触发器
页数 文件大小 规格书
4页 67K
描述
100E SERIES, TRIPLE POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28, PLASTIC, LCC-28

SY100E431JI-TR 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.74
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.48 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:1
位数:1功能数量:3
端子数量:28最高工作温度:85 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240传播延迟(tpd):0.8 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:1100 MHzBase Number Matches:1

SY100E431JI-TR 数据手册

 浏览型号SY100E431JI-TR的Datasheet PDF文件第2页浏览型号SY100E431JI-TR的Datasheet PDF文件第3页浏览型号SY100E431JI-TR的Datasheet PDF文件第4页 
SY10E431  
SY100E431  
FINAL  
3-BIT DIFFERENTIAL  
FLIP-FLOP  
DESCRIPTION  
FEATURES  
Differential D, clock and Q  
The SY10/100E431 are 3-bit flip-flops with differential  
clock, data input and data output.  
Extended 100E VEE range of –4.2V to –5.5V  
VBB output for single-ended use  
The asynchronous Set and Reset controls are edge-  
triggered rather than level controlled. This allows the user  
to rapidly set or reset the flip-flop and then continue  
clocking at the next clock edge without the necessity of  
de-asserting the set/reset signal (as would be the case  
with a level controlled set/reset).  
The E431 is also designed with larger internal swings,  
an approach intended to minimize the time spent crossing  
the threshold region and thus reduces the metastability  
susceptibility window.  
1100MHz min. toggle frequency  
Edge-triggered asynchronous set and reset  
Fully compatible with Motorola MC10E/100E431  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN CONFIGURATION  
PIN NAMES  
Pin  
D[0:2], D[0:2]  
CLK[0:2], CLK[0:2]  
S[0:2]  
Function  
Differential Data Inputs  
Differential Clock Inputs  
Edge Triggered Set Inputs  
Edge Triggered Reset Inputs  
VBB Reference Output  
Differential Data Outputs  
VCC to Output  
(1)  
TRUTH TABLE  
Dn  
L
CLKn  
Rn  
L
Sn  
L
Qn  
L
R[0:2]  
Z
Z
L
L
VBB  
H
X
L
L
H
L
Q[0:2], Q[0:2]  
VCCO  
Z
L
X
L
Z
H
NOTE:  
1. Z = LOW-to-HIGH transition.  
Rev.: D  
Amendment:/0  
Issue Date: November2002  
1

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