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SY100E446JZ PDF预览

SY100E446JZ

更新时间: 2024-11-24 06:15:07
品牌 Logo 应用领域
麦瑞 - MICREL 转换器
页数 文件大小 规格书
9页 85K
描述
4-BIT PARALLEL-TO-SERIAL CONVERTER

SY100E446JZ 数据手册

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6  
4-BIT PARALLEL-TO-SERIAL  
CONVERTER  
SY10E446  
SY100E446  
DESCRIPTION  
FEATURES  
On-chip clock ÷4 and ÷8  
The SY10/100E446 are integrated 4-bit parallel-to-  
serial data converters. These devices are designed to  
operate for NRZ data rates of up to a minimum of 1.3Gb/  
s. The chips generate a divide-by-4 and a divide-by-8  
clock for both 4-bit conversion and a two-chip 8-bit  
conversion function. The conversion sequence was  
chosen to convert the parallel data into a serial stream  
from bit D0 to D3. A serial input is provided to cascade  
two E446 devices for 8-bit conversion applications.  
The SYNC input will asynchronously reset the internal  
clock circuitry. This pin allows the user to reset the internal  
clock conversion unit and, thus, select the start of the  
conversion process.  
Extended 100E VEE range of –4.2V to –5.5V  
1.6Gb/s typical data rate capability  
Differential clock and serial inputs  
VBB output for single-ended use  
Asynchronous data synchronization  
Mode select to expand to 8 bits  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E446  
Available in 28-pin PLCC package  
The MODE input is used to select the conversion mode  
of the device. With the MODE input LOW (or open) the  
device will function as a 4-bit converter. When the mode  
input is driven HIGH, the internal load clock will change  
on every eighth clock cycle, thus allowing for an 8-bit  
conversion scheme using two E446s. When cascaded in  
an 8-bit conversion scheme, the devices will not operate  
at the 1.3Gb/s data rate of a single device. Refer to the  
applications section of this data sheet for more information  
on cascading the E446.  
For lower data rate applications, a VBB reference  
voltage is supplied for single-ended inputs. When  
operating at clock rates above 500MHz, differential input  
signals are recommended. For single-ended inputs, the  
VBB pin is tied to the inverting differential input and  
bypassed via a 0.01µF capacitor. The VBB provides the  
switching reference for the input differential amplifier. The  
VBB can also be used to AC couple an input signal.  
PIN NAMES  
Pin  
SIN, SIN  
D0 – D3  
Function  
Differential Serial Data Input  
Parallel Data Input  
SOUT, SOUT  
CLK, CLK  
CL/4, CL/4  
CL/8, CL/8  
MODE  
Differential Serial Data Output  
Differential Clock Input  
Differential 4 Clock Output  
Differential 8 Clock Output  
Conversion Mode, 4-bit/8-bit  
Conversion Synchronizing Input  
VCC to Output  
SYNC  
VCCO  
Rev.: F  
Amendment:/0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

SY100E446JZ 替代型号

型号 品牌 替代类型 描述 数据表
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