SY100E452JI

更新时间： 2024-01-18 01:21:56

品牌	Logo	应用领域
麦瑞 - MICREL		触发器锁存器逻辑集成电路
页数	文件大小	规格书
4页	66K
描述
5-BIT DIFFERENTIAL REGISTER

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技术参数
数据手册

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SY100E452JI 技术参数

生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.33	Is Samacsys：	N
其他特性：	WITH DIFFERENTIAL CLOCK	系列：	100E
JESD-30 代码：	S-PQCC-J28	长度：	11.48 mm
逻辑集成电路类型：	D FLIP-FLOP	位数：	5
功能数量：	1	端子数量：	28
输出极性：	COMPLEMENTARY	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	传播延迟（tpd）：	0.8 ns
座面最大高度：	4.57 mm	表面贴装：	YES
技术：	ECL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
触发器类型：	POSITIVE EDGE	宽度：	11.48 mm
最小 fmax：	1100 MHz	Base Number Matches：	1

SY100E452JI 数据手册

5-BIT DIFFERENTIAL

SY10E452

SY100E452

DESCRIPTION

FEATURES

■ Differential D, CLK and Q

The SY10/100E452 are 5-bit differential registers with

differential data (inputs and outputs) and clock. The

registers are triggered by a positive transition of the

positive clock (CLK) input. A high on the Master Reset

(MR) asynchronously resets all registers so that the Q

outputs go LOW.

■ Extended 100E VEE range of –4.2V to –5.5V

■ VBB output for single-ended use

■ 1100MHz min. toggle frequency

■ Asynchronous Master Reset

The differential input structures are clamped so that

the inputs of unused registers can be left open without

upsetting the bias network of the devices. The clamping

action will assert the /D and the /CLK sides of the inputs.

Because of the edge-triggered flip-flop nature of the

devices, simultaneously opening both the clock and data

inputs will result in an output which reaches an

unidentified but valid state.

■ Fully compatible with Motorola MC10E/100E452

■ Available in 28-pin PLCC package

The fully differential design of the devices makes them

ideal for very high frequency applications where a

registered data path is necessary.

BLOCK DIAGRAM

PIN CONFIGURATION

24 23 22 21 20 19

CLK

TOP VIEW

PLCC

J28-1

10 11

PIN NAMES

D [0:4], /D [0:4]

Function

Differential Data Inputs

Master Reset Input

Differential Clock Input

VBB Reference Output

Differential Data Outputs

VCC to Output

CLK, /CLK

VBB

CLK

Q [0:4], Q [0:4]

VCCO

Rev.: D

Amendment:/0

Issue Date: May, 1999

12 3 4

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