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SY100E457JZTR PDF预览

SY100E457JZTR

更新时间: 2024-11-20 03:09:07
品牌 Logo 应用领域
麦瑞 - MICREL 解复用器逻辑集成电路
页数 文件大小 规格书
4页 63K
描述
TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

SY100E457JZTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.36系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:MULTIPLEXER
湿度敏感等级:2功能数量:3
输入次数:2输出次数:1
端子数量:28最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:-4.5 V
最大电源电流(ICC):127 mAProp。Delay @ Nom-Sup:0.7 ns
传播延迟(tpd):0.7 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Multiplexer/Demultiplexers
表面贴装:YES技术:ECL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:11.48 mmBase Number Matches:1

SY100E457JZTR 数据手册

 浏览型号SY100E457JZTR的Datasheet PDF文件第2页浏览型号SY100E457JZTR的Datasheet PDF文件第3页浏览型号SY100E457JZTR的Datasheet PDF文件第4页 
7  
TRIPLE DIFFERENTIAL  
2:1 MULTIPLEXER  
SY10E457  
SY100E457  
DESCRIPTION  
FEATURES  
Differential D and Q  
The SY10/100E457 are 3-bit differential 2:1  
multiplexers. The fully differential data path makes the  
devices ideal for multiplexing low skew clock or other  
skew sensitive signals. Multiple VBB pins are provided to  
ease AC coupling input signals.  
The higher frequency outputs provide the device with  
a >1.0GHz bandwidth to meet the needs of the most  
demanding system clock.  
Extended 100E VEE range of –4.2V to –5.5V  
VBB output for single-ended use  
700ps max. propagation delay  
High frequency outputs  
Separate and common select  
Internal 75Kinput pulldown resistors  
Available in 28-pin PLCC package  
Both separate selects and a common select are  
provided to make the device well suited for both data  
path and random logic applications.  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
Dn[0:2], Dn[0:2]  
SEL  
Function  
Differential Data Inputs  
Individual Select Input  
Common Select Input  
VBB Reference Output  
Differential Data Outputs  
VCC to Output  
D
D
0a  
0a  
H
2:1  
MUX  
Q
Q
0
0
D
D
0b  
0b  
L
COMSEL  
VBB  
SEL  
0
Q[0:2], Q[0:2]  
VCCO  
D
D
1a  
1a  
H
2:1  
MUX  
Q
Q
1
1
D
D
1b  
1b  
L
SEL  
1
D
D
2a  
2a  
H
2:1  
MUX  
Q
Q
2
2
D
D
2b  
2b  
L
SEL  
2
COMSEL  
V
BB  
Rev.: F  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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