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SY100E457JCTR

更新时间： 2024-11-23 22:17:35

品牌	Logo	应用领域
麦瑞 - MICREL		复用器
页数	文件大小	规格书
4页	64K
描述
TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

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中文翻译

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数据手册

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SY100E457JCTR 数据手册

TRIPLE DIFFERENTIAL

2:1 MULTIPLEXER

SY10E457

SY100E457

DESCRIPTION

FEATURES

■ Differential D and Q

The SY10/100E457 are 3-bit differential 2:1

multiplexers. The fully differential data path makes the

devices ideal for multiplexing low skew clock or other

skew sensitive signals. Multiple VBB pins are provided to

ease AC coupling input signals.

The higher frequency outputs provide the device with

a >1.0GHz bandwidth to meet the needs of the most

demanding system clock.

■ Extended 100E VEE range of –4.2V to –5.5V

■ VBB output for single-ended use

■ 700ps max. propagation delay

■ High frequency outputs

■ Separate and common select

■ Internal 75KΩ input pulldown resistors

■ Available in 28-pin PLCC package

Both separate selects and a common select are

provided to make the device well suited for both data

path and random logic applications.

BLOCK DIAGRAM

PIN CONFIGURATION

2:1

MUX

24 23 22 21 20 19

SEL

SEL1

D1a

VEE

VBB

D1b

VCC

TOP VIEW

PLCC

2:1

MUX

J28-1

10 11

SEL

2:1

MUX

PIN NAMES

SEL

Dn[0:2], Dn[0:2]

SEL

Function

Differential Data Inputs

Individual Select Input

Common Select Input

VBB Reference Output

Differential Data Outputs

VCC to Output

COMSEL

VBB

Q[0:2], Q[0:2]

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

12 3 4

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