5秒后页面跳转
SY100E451JYTR PDF预览

SY100E451JYTR

更新时间: 2024-02-04 09:12:53
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路时钟
页数 文件大小 规格书
4页 63K
描述
6-BIT REGISTER DIFFERENTIAL DATA CLOCK

SY100E451JYTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:QCCJ,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.67
Is Samacsys:N其他特性:WITH DIFFERENTIAL CLOCK
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:D FLIP-FLOP湿度敏感等级:2
位数:6功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260传播延迟(tpd):0.85 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:1100 MHzBase Number Matches:1

SY100E451JYTR 数据手册

 浏览型号SY100E451JYTR的Datasheet PDF文件第2页浏览型号SY100E451JYTR的Datasheet PDF文件第3页浏览型号SY100E451JYTR的Datasheet PDF文件第4页 
6-BIT REGISTER  
DIFFERENTIAL DATA CLOCK  
SY10E451  
SY100E451  
FEATURES  
DESCRIPTION  
1100MHz min. toggle frequency  
Extended 100E VEE range of –4.2V to –5.5V  
Differential inputs: data and clock  
VBB output for single-ended use  
Asynchronous Master Reset  
The SY10/100E451 offer six D-type flip-flops with single-  
ended outputs and differential data and clock inputs,  
designed for use in new, high-performance ECL systems.  
The registers are triggered by the rising edge of the CLK  
input.  
A logic HIGH on the Master Reset (MR) input resets all  
outputs to a logic LOW. The VBB output is provided for use  
as a reference voltage for single-ended reception of ECL  
signals to that device only. When used for this purpose, it  
is recommended that VBB is decoupled to VCC via a 0.01µF  
capacitor.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E451  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
D0–D5  
Function  
+ Data Input  
D0  
/D0  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
D
D
/D0–/D5  
CLK  
– Data Input  
R
R
R
R
R
R
+ Clock Input  
– Clock Input  
Data Outputs  
Master Reset Input  
VBB Output  
D1  
/D1  
/CLK  
Q0–Q5  
MR  
D2  
/D2  
D
D
D
D
VBB  
VCCO  
VCC to Output  
D3  
/D3  
D4  
/D4  
D5  
/D5  
CLK  
/CLK  
MR  
VBB  
Rev.: G  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

与SY100E451JYTR相关器件

型号 品牌 描述 获取价格 数据表
SY100E451JY-TR MICREL D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28

获取价格

SY100E451JY-TR MICROCHIP D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28

获取价格

SY100E452JC MICREL 5-BIT DIFFERENTIAL REGISTER

获取价格

SY100E452JCTR MICREL 5-BIT DIFFERENTIAL REGISTER

获取价格

SY100E452JI MICREL 5-BIT DIFFERENTIAL REGISTER

获取价格

SY100E452JI MICROCHIP SY100E452JI

获取价格