SY100E451JYTR

更新时间： 2024-11-20 05:04:31

品牌	Logo	应用领域
麦瑞 - MICREL		触发器逻辑集成电路时钟
页数	文件大小	规格书
4页	63K
描述
6-BIT REGISTER DIFFERENTIAL DATA CLOCK

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中文翻译

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数据手册

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SY100E451JYTR 数据手册

SY10E451

SY100E451

Micrel, Inc.

6-BIT REGISTER

DIFFERENTIAL DATA CLOCK

SY10E451

SY100E451

FEATURES

DESCRIPTION

■ 1100MHz min. toggle frequency

■ Extended 100E V_EErange of –4.2V to –5.5V

■ Differential inputs: data and clock

■ V_BBoutput for single-ended use

■ Asynchronous Master Reset

The SY10/100E451 offer six D-type flip-flops with single-

ended outputs and differential data and clock inputs,

designed for use in new, high-performance ECL systems.

The registers are triggered by the rising edge of the CLK

input.

A logic HIGH on the Master Reset (MR) input resets all

outputs to a logic LOW. The V_BBoutput is provided for use

as a reference voltage for single-ended reception of ECL

signals to that device only. When used for this purpose, it

is recommended that V_BBis decoupled to V_CCvia a 0.01µF

capacitor.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E451

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

PIN NAMES

D0–D5

Function

+ Data Input

D₀

/D₀

Q₀

Q₁

Q₂

Q₃

Q₄

Q₅

/D0–/D5

CLK

– Data Input

+ Clock Input

– Clock Input

Data Outputs

Master Reset Input

V_BBOutput

D₁

/D₁

/CLK

Q0–Q5

D₂

/D₂

V_BB

V_CCO

V_CCto Output

D₃

/D₃

D₄

/D₄

D₅

/D₅

CLK

/CLK

V_BB

Rev.: G

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4

中文翻译

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