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SY100E451JY PDF预览

SY100E451JY

更新时间: 2024-02-29 08:50:18
品牌 Logo 应用领域
美国微芯 - MICROCHIP 逻辑集成电路触发器
页数 文件大小 规格书
4页 96K
描述
D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28

SY100E451JY 技术参数

是否无铅: 不含铅生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCJ,
针数:28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.17
其他特性:WITH DIFFERENTIAL CLOCK系列:100E
JESD-30 代码:S-PQCC-J28长度:11.48 mm
逻辑集成电路类型:D FLIP-FLOP位数:6
功能数量:1端子数量:28
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):0.8 ns
座面最大高度:4.57 mm表面贴装:YES
技术:ECL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:1100 MHzBase Number Matches:1

SY100E451JY 数据手册

 浏览型号SY100E451JY的Datasheet PDF文件第2页浏览型号SY100E451JY的Datasheet PDF文件第3页浏览型号SY100E451JY的Datasheet PDF文件第4页 
NOT RECOMMENDED FOR NEW DESIGNS  
6-BIT REGISTER  
DIFFERENTIAL DATA CLOCK  
SY10E451  
SY100E451  
FEATURES  
DESCRIPTION  
1100MHz min. toggle frequency  
Extended 100E VEE range of –4.2V to –5.5V  
Differential inputs: data and clock  
VBB output for single-ended use  
Asynchronous Master Reset  
The SY10/100E451 offer six D-type flip-flops with single-  
ended outputs and differential data and clock inputs,  
designed for use in new, high-performance ECL systems.  
The registers are triggered by the rising edge of the CLK  
input.  
A logic HIGH on the Master Reset (MR) input resets all  
outputs to a logic LOW. The VBB output is provided for use  
as a reference voltage for single-ended reception of ECL  
signals to that device only. When used for this purpose, it  
is recommended that VBB is decoupled to VCC via a 0.01µF  
capacitor.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E451  
Available in 28-pin PLCC package  
BLOCK DIAGRAM  
PIN NAMES  
Pin  
D0–D5  
Function  
+ Data Input  
D0  
/D0  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
D
D
/D0–/D5  
CLK  
– Data Input  
R
R
R
R
R
R
+ Clock Input  
– Clock Input  
Data Outputs  
Master Reset Input  
VBB Output  
D1  
/D1  
/CLK  
Q0–Q5  
MR  
D2  
/D2  
D
D
D
D
VBB  
VCCO  
VCC to Output  
D3  
/D3  
D4  
/D4  
D5  
/D5  
CLK  
/CLK  
MR  
VBB  
Rev.: G  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

SY100E451JY 替代型号

型号 品牌 替代类型 描述 数据表
SY100E452JI MICROCHIP

完全替代

SY100E452JI
SY100E131JY MICROCHIP

完全替代

100E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28

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