SY100E445

更新时间： 2024-02-29 20:46:37

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
8页	84K
描述
4-BIT SERIAL-to-PARALLEL CONVERTER

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SY100E445 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.53	其他特性：	COMPLEMENTARY SERIAL OUTPUT AVAILABLE
计数方向：	RIGHT	系列：	100E
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e3
长度：	11.48 mm	逻辑集成电路类型：	SERIAL IN PARALLEL OUT
湿度敏感等级：	2	位数：	4
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	2.1 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	表面贴装：	YES
技术：	ECL	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	触发器类型：	POSITIVE EDGE
宽度：	11.48 mm	最小 fmax：	2500 MHz
Base Number Matches：	1

SY100E445 数据手册

SY10E445

Micrel, Inc.

SY100E445

4-BIT SERIAL-to-PARALLEL

CONVERTER

SY10E445

SY100E445

FEATURES

DESCRIPTION

■ On-chip clock ÷4 and ÷8

The SY10/100E445 are integrated 4-bit serial-to-parallel

data converters. The devices are designed to operate for

NRZ data rates of up to 2.5Gb/s. The chip generates a

divide-by-4 and a divide-by-8 clock for both 4-bit conversion

and a two-chip 8-bit conversion function. The conversion

sequence was chosen to convert the first serial bit to Q0,

the second to Q1, etc.

Two selectable serial inputs provide a loopback capability

for testing purposes when the device is used in conjunction

with the E446 parallel-to-serial converter.

The start bit for conversion can be moved using the

SYNC input. A single pulse, applied asynchronously for at

least two input clock cycles, shifts the start bit for conversion

from Qn to Qn-1 by one bit. For each additional shift required,

an additional pulse must be applied to the SYNC input.

Asserting the SYNC input will force the internal clock dividers

to "swallow" a clock pulse, effectively shifting a bit from the

Qn to the Qn-1 output (see Timing Diagram B).

The MODE input is used to select the conversion mode

of the device. With the MODE input LOW (or open) the

device will function as a 4-bit converter. When the mode

input is driven HIGH, the data on the output will change on

every eighth clock cycle, thus allowing for an 8-bit conversion

scheme using two E445s. When cascaded in an 8-bit

conversion scheme, the devices will not operate at the

2.5Gb/s data rate of a single device. Refer to the applications

section of this data sheet for more information on cascading

the E445.

■ Extended 100E VEE range of –4.2V to –5.5V

■ 2.5Gb/s data rate capability

■ Differential clock and serial inputs

■ VBB output for single-ended use

■ Asynchronous data synchronization

■ Mode select to expand to 8 bits

■ Internal 75kΩ input pull-down resistors

■ Fully compatible with Motorola MC10E/100E445

■ Available in 28-pin PLCC package

PIN NAMES

SINA, SINA

SINB, SINB

SEL

Function

Differential Serial Data Input A

Differential Serial Data Input B

Serial Input Select Pin

SOUT, SOUT

Q0–Q3

Differential Serial Data Output

Parallel Data Outputs

CLK, CLK

CL/4, CL/4

CL/8, CL/8

MODE

Differential Clock Inputs

Differential ÷4 Clock Output

Differential ÷8 Clock Output

Conversion Mode 4-bit/8-bit

Conversion Synchronizing Input

Input, Resets the Counters

VCC to Output

For lower data rate applications, a VBB reference voltage

is supplied for single-ended inputs. When operating at clock

rates above 500MHz, differential input signals are

recommended. For single-ended inputs, the VBB pin is tied

to the inverting differential input and bypassed via a 0.01µF

capacitor. The VBB provides the switching reference for the

input differential amplifier. The VBB can also be used to AC

couple an input signal.

SYNC

RESET

VCCO

Rev.: F

Amendment:/0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5 6 7 8

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