SY100E445

更新时间： 2024-02-01 09:17:10

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
8页	84K
描述
4-BIT SERIAL-to-PARALLEL CONVERTER

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SY100E445 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.53	其他特性：	COMPLEMENTARY SERIAL OUTPUT AVAILABLE
计数方向：	RIGHT	系列：	100E
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e3
长度：	11.48 mm	逻辑集成电路类型：	SERIAL IN PARALLEL OUT
湿度敏感等级：	2	位数：	4
功能数量：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
传播延迟（tpd）：	2.1 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	表面贴装：	YES
技术：	ECL	温度等级：	OTHER
端子面层：	Matte Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	触发器类型：	POSITIVE EDGE
宽度：	11.48 mm	最小 fmax：	2500 MHz
Base Number Matches：	1

SY100E445 数据手册

SY10E445

SY100E445

Micrel, Inc.

LAOPGPLICICDAITAIGORNASMINFORMATION

Clock

The SY10/100E are integrated 1:4 serial-to-parallel

converters. The chips are designed to work with the

E446 devices to provide both transmission and receiving

of a high-speed serial data path. The E445, under special

input conditions, can convert up to a 2.5Gb/s NRZ data

stream into 4-bit parallel data. The device also provides

a divide-by-four clock output to be used to synchronize

the parallel data with the rest of the system.

E445a

E445b

SIN

SOUT

SIN

Serial Input

Data

The E445 features multiplexed dual serial inputs to

provide test loop capability when used in conjunction

with the E446. Figure 1 illustrates the loop test

architecture. The architecture allows for the electrical

testing of the link without requiring actual transmission

over the serial data path medium. The SINA serial input

of the E445 has an extra buffer delay and, thus, should

be used as the loop back serial input.

Parallel Output Data

100ps

Clock

Tpd CLK

to SOUT

800ps

SOUT

To Serial

Medium

1050ps

SOUT

Parallel

Data

Figure 2. Cascaded 1:8 Converter Architecture

clock-to-serial-out would potentially cause a serial bit to

be swallowed (Figure 3). With a minimum delay of 800ps

on this output, the clock for the lower order E445 cannot

be delayed more than 800ps relative to the clock of the

first E445 without potentially missing a bit of information.

Because the set-up time on the serial input pin is

negative, coincident excursions on the data and clock

inputs of the E445 will result in correct operation.

SINA

Parallel

Data

SINB

From Serial

Medium

Figure 1. Loop Test Architecture

Clock a

Clock b

The E445 features a differential serial output and a

divide-by-8 clock output to facilitate the cascading of two

devices to build a 1:8 demultiplexer. Figure 2 illustrates

the architecture of a 1:8 demultiplexer using two E445s.

The timing diagram for this configuration can be found

on the following page. Notice the serial outputs (SOUT)

of the lower order converter feed the serial inputs of the

higher order device. This feedthrough of the serial inputs

bounds the upper end of the frequency of operation. The

clock-to-serial output propagation delay, plus the set-up

Tpd CLK

to SOUT

800ps

1050ps

Figure 3. Cascade Frequency Limitation

Perhaps the easiest way to delay the second clock

time of the serial input pins, must fit into a single clock relative to the first is to take advantage of the differential

period for the cascade architecture to function properly. clock inputs of the E445. By connecting the clock for the

Using the worst case values for these two parameters second E445 to the complimentary clock input pin, the

from the data sheet, tPD CLK to SOUT = 1150ps or a device will clock a half a clock period after the first E445

clock frequency of 950MHz.

(Figure 4). Utilizing this simple technique will raise the

The clock frequency is significantly lower than that of potential conversion frequency up to 1.5GHz. The divide-

a single converter. To increase this frequency, some by-eight clock of the second E445 should be used to

games can be played with the clock input of the higher synchronize the parallel data to the rest of the system as

order E445. By delaying the clock feeding the second the parallel data of the two E445s will no longer be

E445 relative to the clock of the first E445, the frequency synchronized. This skew problem between the outputs

of operation can be increased. The delay between the can be worked around as the parallel information will be

two clocks can be increased until the minimum delay of static for eight more clock pulses.

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

1 2 3 456 7 8

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