SY100E446JC

更新时间： 2024-02-24 07:00:16

品牌	Logo	应用领域
麦瑞 - MICREL		转换器移位寄存器触发器逻辑集成电路
页数	文件大小	规格书
8页	85K
描述
4-BIT PARALLEL-TO-SERIAL CONVERTER

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SY100E446JC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.53	Is Samacsys：	N
其他特性：	SISO OPERATION ALSO AVAILABLE	计数方向：	RIGHT
系列：	100E	JESD-30 代码：	S-PQCC-J28
JESD-609代码：	e3	长度：	11.48 mm
逻辑集成电路类型：	PARALLEL IN SERIAL OUT	湿度敏感等级：	2
位数：	4	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：		输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	1.7 ns
认证状态：	Not Qualified	座面最大高度：	4.57 mm
表面贴装：	YES	技术：	ECL
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
触发器类型：	NEGATIVE EDGE	宽度：	11.48 mm
最小 fmax：	1300 MHz	Base Number Matches：	1

SY100E446JC 数据手册

4-BIT PARALLEL-TO-SERIAL

CONVERTER

SY10E446

SY100E446

DESCRIPTION

FEATURES

■ On-chip clock ÷4 and ÷8

The SY10/100E446 are integrated 4-bit parallel-to-

serial data converters. These devices are designed to

operate for NRZ data rates of up to a minimum of 1.3Gb/

s. The chips generate a divide-by-4 and a divide-by-8

clock for both 4-bit conversion and a two-chip 8-bit

conversion function. The conversion sequence was

chosen to convert the parallel data into a serial stream

from bit D0 to D3. A serial input is provided to cascade

two E446 devices for 8-bit conversion applications.

The SYNC input will asynchronously reset the internal

clock circuitry. This pin allows the user to reset the internal

clock conversion unit and, thus, select the start of the

conversion process.

■ Extended 100E VEE range of –4.2V to –5.5V

■ 1.6Gb/s typical data rate capability

■ Differential clock and serial inputs

■ VBB output for single-ended use

■ Asynchronous data synchronization

■ Mode select to expand to 8 bits

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E446

■ Available in 28-pin PLCC package

The MODE input is used to select the conversion mode

of the device. With the MODE input LOW (or open) the

device will function as a 4-bit converter. When the mode

input is driven HIGH, the internal load clock will change

on every eighth clock cycle, thus allowing for an 8-bit

conversion scheme using two E446s. When cascaded in

an 8-bit conversion scheme, the devices will not operate

at the 1.3Gb/s data rate of a single device. Refer to the

applications section of this data sheet for more information

on cascading the E446.

For lower data rate applications, a VBB reference

voltage is supplied for single-ended inputs. When

operating at clock rates above 500MHz, differential input

signals are recommended. For single-ended inputs, the

VBB pin is tied to the inverting differential input and

bypassed via a 0.01µF capacitor. The VBB provides the

switching reference for the input differential amplifier. The

VBB can also be used to AC couple an input signal.

PIN CONFIGURATION

24 23 22 21 20 19

CLK

VCC

VBB

TOP VIEW

PLCC

SOUT

VEE

J28-1

SIN

VCCO

SYNC

10 11

PIN NAMES

SIN, SIN

D0 – D3

Function

Differential Serial Data Input

Parallel Data Input

SOUT, SOUT

CLK, CLK

CL/4, CL/4

CL/8, CL/8

MODE

Differential Serial Data Output

Differential Clock Input

Differential 4 Clock Output

Differential 8 Clock Output

Conversion Mode, 4-bit/8-bit

Conversion Synchronizing Input

VCC to Output

SYNC

VCCO

Rev.: C

Amendment:/1

Issue Date: February, 1998

12 3 4 5 6 7 8

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