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SY100E431JZ PDF预览

SY100E431JZ

更新时间: 2024-11-20 05:04:31
品牌 Logo 应用领域
麦瑞 - MICREL 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 63K
描述
3-BIT DIFFERENTIAL FLIP-FLOP

SY100E431JZ 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:LEAD FREE, PLASTIC, LCC-28针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.48 mm
逻辑集成电路类型:D FLIP-FLOP位数:1
功能数量:3端子数量:28
最高工作温度:85 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):0.8 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:11.48 mm最小 fmax:1100 MHz
Base Number Matches:1

SY100E431JZ 数据手册

 浏览型号SY100E431JZ的Datasheet PDF文件第2页浏览型号SY100E431JZ的Datasheet PDF文件第3页浏览型号SY100E431JZ的Datasheet PDF文件第4页 
1  
3-BIT DIFFERENTIAL  
FLIP-FLOP  
SY10E431  
SY100E431  
DESCRIPTION  
FEATURES  
Differential D, clock and Q  
The SY10/100E431 are 3-bit flip-flops with differential  
clock, data input and data output.  
Extended 100E VEE range of –4.2V to –5.5V  
VBB output for single-ended use  
The asynchronous Set and Reset controls are edge-  
triggered rather than level controlled. This allows the user  
to rapidly set or reset the flip-flop and then continue  
clocking at the next clock edge without the necessity of  
de-asserting the set/reset signal (as would be the case  
with a level controlled set/reset).  
The E431 is also designed with larger internal swings,  
an approach intended to minimize the time spent crossing  
the threshold region and thus reduces the metastability  
susceptibility window.  
1100MHz min. toggle frequency  
Edge-triggered asynchronous set and reset  
Fully compatible with Motorola MC10E/100E431  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
S
0
Pin  
D[0:2], D[0:2]  
CLK[0:2], CLK[0:2]  
S[0:2]  
Function  
Differential Data Inputs  
Differential Clock Inputs  
Edge Triggered Set Inputs  
Edge Triggered Reset Inputs  
VBB Reference Output  
Differential Data Outputs  
VCC to Output  
S
R
D
D
0
0
D
D
D
Q
Q
Q
Q
0
0
CLK  
CLK  
0
0
R[0:2]  
VBB  
R
0
Q[0:2], Q[0:2]  
VCCO  
S1  
S
R
D
D
1
1
Q
Q
Q
Q
1
1
CLK  
CLK  
1
1
(1)  
TRUTH TABLE  
Dn  
L
CLKn  
Rn  
L
Sn  
L
Qn  
L
R
1
Z
Z
L
L
S2  
H
X
L
L
H
L
S
R
D
D
2
2
Q
Q
Q
Q
2
2
Z
L
X
L
Z
H
CLK  
CLK  
2
2
NOTE:  
1. Z = LOW-to-HIGH transition.  
R
2
VBB  
Rev.: E  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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