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SN74SSQE32882ZALR PDF预览

SN74SSQE32882ZALR

更新时间: 2024-11-06 07:03:55
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路测试双倍数据速率
页数 文件大小 规格书
8页 336K
描述
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER

SN74SSQE32882ZALR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:BGA
包装说明:NFBGA-176针数:176
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.97
Is Samacsys:N系列:S
输入调节:STANDARDJESD-30 代码:R-PBGA-B176
JESD-609代码:e1长度:13.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:176实输出次数:
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA176,11X20,25封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:1.5 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Logic ICs标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.65 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

SN74SSQE32882ZALR 数据手册

 浏览型号SN74SSQE32882ZALR的Datasheet PDF文件第2页浏览型号SN74SSQE32882ZALR的Datasheet PDF文件第3页浏览型号SN74SSQE32882ZALR的Datasheet PDF文件第4页浏览型号SN74SSQE32882ZALR的Datasheet PDF文件第5页浏览型号SN74SSQE32882ZALR的Datasheet PDF文件第6页浏览型号SN74SSQE32882ZALR的Datasheet PDF文件第7页 
SN74SSQE32882  
www.ti.com .................................................................................................................................................................................................. SCAS857MARCH 2008  
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST  
ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER  
First, when the QCSEN input pin is open or pulled  
high, the component has two chip select inputs,  
1
FEATURES  
2
1-to-2 Register Outputs and 1-to-4 Clock Pair  
Outputs Support Stacked DDR3 DIMMs  
DCS0 and DCS1, and two copies of each chip select  
output, QACS0, QACS1, QBCS0 and QBCS1. This  
mode is the QuadCS disabled mode. Alternatively,  
when the QCSEN input pin is pulled low, the  
component has four chip select inputs DCS[3:0], and  
four chip select outputs, QCS[3:0]. This mode is the  
QuadCS enabled mode.  
Chip Select Inputs Prevent Data Outputs from  
Changing State and Minimize System Power  
Consumption  
1.5-V Phase Lock Loop Clock Driver Buffers  
One Differential Clock Pair (CK and CK) and  
Distributes to Four Differential Outputs  
When QCSEN is high or floating, the device also  
supports an operating mode that allows a single  
device to be mounted on the back side of a DIMM  
array. This device can then be configured to keep the  
input bus termination (IBT) feature enabled for all  
input signals independent of MIRROR. The  
SN74SSQE32882. operates from a differential clock  
(CK and CK). Data are registered at the crossing of  
CK going high and CK going low. This data can either  
be re-driven to the outputs or used to access internal  
control registers. Details are covered in the Function  
Tables (each flip-flop) with QCSEN = low.  
1.5-V CMOS Inputs  
Checks Parity on Command and Address  
(CS-gated) Data Inputs  
Supports LVCMOS Switching Levels on  
RESET Input  
RESET Input:  
Disables Differential Input Receivers  
Resets All Registers  
Forces All Outputs into Pre-defined States  
Input bus data integrity is protected by a parity  
function. All address and command input signals are  
summed; the last bit of the sum is then compared to  
the parity signal delivered by the system at the  
PAR_IN input one clock cycle later. If these two  
values do not match, the device pulls the open drain  
output ERROUT low. The control signals (DCKE0,  
DCKE1, DODT0, DODT1, and DCS[n:0]) are not part  
of this computation.  
Optimal Pinout for DDR3 DIMM PCB Layout  
Supports Four Chip Selects  
Single Register Backside Mount Support  
APPLICATIONS  
DDR3-Registered DIMMs  
Quad-Rank RDIMM  
DESCRIPTION/ORDERING INFORMATION  
The  
SN74SSQE32882  
implements  
different  
power-saving mechanisms to reduce thermal power  
dissipation and to support system power-down states.  
Power consumption is further reduced by disabling  
unused outputs.  
This JEDEC standard, 28-bit 1:2 or 26-bit 1:2 and  
4-bit 1:1 registering clock driver with parity is  
designed for operation on DDR3-registered DIMMs  
with VDD of 1.5 V.  
The package design is optimal for high-density  
DIMMs. By aligning input and output positions  
towards DIMM finger-signal ordering and SDRAM  
ballout, the device de-scrambles the DIMM traces  
and allows low crosstalk designs with low  
interconnect latency. Edge-controlled outputs reduce  
ringing and improve signal eye opening at the  
SDRAM inputs.  
All inputs are 1.5-V, CMOS-compatible. All outputs  
are 1.5-V CMOS drivers optimized to drive DRAM  
signals on terminated traces in DDR3 RDIMM  
applications. Clock outputs Yn and Yn and control net  
outputs DxCKEn, DxCSn, and DxODTn can each be  
driven with a different strength and skew to optimize  
signal integrity, compensate for different loading, and  
balance signal travel speed.  
Throughout this document, DCS[n:0] indicates all of  
the chip select inputs, where n = 1 for QuadCS  
disabled, and n = 3 for QuadCS enabled. QxCS[n:0]  
indicates all of the chip select outputs.  
The SN74SSQE32882 has two basic modes of  
operation associated with the Quad Chip Select  
Enable (QCSEN) input.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
Copyright © 2008, Texas Instruments Incorporated  

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