Datasheet > SN74SSQEC32882

SN74SSQEC32882

更新时间： 2024-11-06 12:21:43

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器测试
页数	文件大小	规格书
9页	498K
描述
28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

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SN74SSQEC32882 数据手册

SN74SSQEC32882

www.ti.com

SCAS920-PUB –NOVEMBER 2011

28-Bit to 56-Bit Registered Buffer With Address Parity Test

One Pair to Four Pair Differential Clock PLL Driver

Check for Samples: SN74SSQEC32882

FEATURES

(CS-Gated) Data Inputs

•

Configurable Driver Strength

Uses Internal Feedback Loop

Optimized Power Consumption

•

JEDEC SSTE32882

1-to-2 Register Outputs and 1-to-4 Clock Pair

Outputs Support Stacked DDR3 RDIMMs

•

CKE Powerdown Mode for Optimized System

Power Consumption

APPLICATIONS

1.5V/1.35V/1.25V Phase Lock Loop Clock

Driver for Buffering One Differential Clock Pair

(CK and CK) and Distributing to Four

Differential Outputs

•

DDR3 Registered DIMMs up to DDR3-1866

DDR3L Registered DIMMs up to DDR3L-1600

DDR3U Registered DIMMs up to DDR3U-1333

Single-, Dual- and Quad-Rank RDIMM

•

1.5V/1.35V/1.25V CMOS Inputs

Checks Parity on Command and Address

DESCRIPTION

This 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3

registered DIMMs with V_DDof 1.5 V, on DDR3L registered DIMMs with V_DDof 1.35 V and on DDR3U registered

DIMMs with V_DDof 1.25 V.

All inputs are 1.5 V, 1.35V and 1.25 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM

signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs

DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity,

compensate for different loading and equalize signal travel speed.

The SN74SSQEC32882 has two basic modes of operation associated with the Quad Chip Select Enable

(QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs,

DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the

"QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs

DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of

this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for

QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.

The device also supports a mode where a single device can be mounted on the back side of a DIMM. If

MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.

The SN74SSQEC32882 operates from a differential clock (CK and CK). Data are registered at the crossing of

CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to

access device internal control registers.

The input bus data integrity is protected by a parity function. All address and command input signals are added

up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one

clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals

(DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.

The SN74SSQEC32882 implements different power saving mechanisms to reduce thermal power dissipation and

to support system power down states. By disabling unused outputs the power consumption is further reduced.

The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM

finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk

design with low interconnect latency.

Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...9

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与SN74SSQEC32882相关器件

型号	品牌	获取价格	描述	数据表
SN74SSQEC32882ZALR	TI	获取价格	28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differen
SN74SSTE32882	TI	获取价格	28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Diff
SN74SSTE32882ZALR	TI	获取价格	28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Diff
SN74SSTEB32866	TI	获取价格	1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
SN74SSTEB32866ZWLR	TI	获取价格	1.5V/1.8V 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
SN74SSTL16837	TI	获取价格	20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74SSTL16837A	TI	获取价格	20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74SSTL16837ADGG	TI	获取价格	20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74SSTL16837ADGGR	TI	获取价格	SSTL SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
SN74SSTL16847	TI	获取价格	20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS

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