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SN74SSTL32867GKER PDF预览

SN74SSTL32867GKER

更新时间： 2024-11-06 21:22:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
5页 431K
描述
SSTL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, FBGA-96

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SN74SSTL32867GKER 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：LFBGA,针数：96
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：SSTL
JESD-30 代码：R-PBGA-B96长度：13.5 mm
逻辑集成电路类型：D FLIP-FLOP位数：26
功能数量：1端子数量：96
最高工作温度：70 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH传播延迟（tpd）：3.8 ns
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：COMMERCIAL端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
触发器类型：POSITIVE EDGE宽度：5.5 mm
Base Number Matches：1

SN74SSTL32867GKER 数据手册

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SN74SSTL32867  
DESIGNGOAL  
26-BIT REGISTERED BUFFER  
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS  
SCES240A – APRIL 1999 – REVISED MAY 1999  
D
Member of the Texas Instruments  
Widebus Family  
D
D
Differential CLK Signal  
Advanced ULTTL Output Circuitry  
Eliminates Switching Noise in  
Unterminated Line  
D
Supports SSTL_2 Signal Data Inputs  
D
Supports LVTTL Switching Levels on the  
RESET Pin  
D
Packaged in Plastic Fine-Pitch  
Ball-Grid-Array Package  
D
Flow-Through Architecture Optimizes PCB  
Layout  
description  
This 26-bit registered buffer is designed for 2.3-V to 2.7-V V  
LVCMOS-output applications.  
operation and SSTL_2 input and unterminated  
CC  
Data flow from A to Y is controlled by differential clock (CLK, CLK) inputs and the LVTTL reset (RESET) input.  
Data are triggered on the positive edge of the positive clock (CLK). The negative clock (CLK) is used to maintain  
noise margins. When RESET is low, all registers are reset, and all outputs are low.  
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in  
the low state during power up.  
The SN74SSTL32867 is characterized for operation from 0°C to 70°C.  
GKE PACKAGE  
(TOP VIEW)  
terminal assignments  
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A1  
V
GND  
V
Y1  
Y2  
Y4  
Y6  
Y8  
CC  
DDQ  
A
B
C
D
A3  
A2  
A4  
V
REF  
NC  
GND  
GND  
Y3  
A5  
Y5  
A7  
A6  
GND  
V
DDQ  
GND  
Y7  
A9  
A8  
V
CC  
GND  
Y9  
V
DDQ  
E
F
G
H
J
A11  
A13  
A15  
CLK  
CLK  
A16  
A18  
A20  
A22  
A24  
A26  
A10  
A12  
A14  
NC  
V
DDQ  
Y10  
Y12  
GND  
GND  
Y15  
Y17  
Y18  
Y20  
Y22  
Y24  
Y26  
GND  
Y11  
G
H
J
V
CC  
V
DDQ  
GND  
GND  
GND  
GND  
Y13  
Y14  
Y16  
GND  
K
L
RESET  
A17  
A19  
A21  
A23  
A25  
V
CC  
V
DDQ  
GND  
V
DDQ  
K
L
M
N
P
R
T
V
CC  
GND  
V
DDQ  
Y19  
GND  
NC  
V
DDQ  
GND  
M
N
P
R
T
Y21  
Y23  
Y25  
NC  
GND  
V
CC  
GND  
V
DDQ  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
6–21  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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