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SN74SSTU32866

更新时间： 2024-11-06 04:51:07
品牌 Logo 应用领域
德州仪器 - TI 双倍数据速率
页数 文件大小 规格书
37页 715K
描述
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

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SN74SSTU32866 数据手册

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SCES564 − APRIL 2004  
D
Member of the Texas Instruments  
Widebus+Family  
Pinout Optimizes DDR2 DIMM PCB Layout  
D
D
D
Checks Parity on DIMM-Independent Data  
Inputs  
D
Able to Cascade with a Second  
SN74SSTU32866  
D
Configurable as 25-Bit 1:1 or 14-Bit 1:2  
Registered Buffer  
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and  
Forces All Outputs Low, Except QERR  
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Chip-Select Inputs Gate the Data Outputs  
from Changing State and Minimizes System  
Power Consumption  
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Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Output Edge-Control Circuitry Minimizes  
Switching Noise in an Unterminated Line  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Supports SSTL_18 Data Inputs  
Differential Clock (CLK and CLK) Inputs  
− 1000-V Charged-Device Model (C101)  
Supports LVCMOS Switching Levels on the  
Control and RESET Inputs  
description/ordering information  
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V  
operation. In the  
CC  
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout  
configuration, two devices per DIMM are required to drive 18 SDRAM loads.  
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are  
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the  
open-drain error (QERR) output.  
The SN74SSTU32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing  
of CLK going high and CLK going low.  
The SN74SSTU32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,  
compares it with the data received on the DIMM-independent D-inputs (D2−D3, D5−D6, D8−D25 when  
C0 = 0 and C1 = 0; D2−D3, D5−D6, D8−D14 when C0 = 0 and C1=1; or D1−D6, D8−D13 when C0 = 1 and  
C1=1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The  
convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent  
data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be  
tied to a known logic state.  
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the  
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the  
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
PACKAGE  
LFBGA − GKE  
A
0°C to 70°C  
Tape and reel SN74SSTU32866GKER  
SU866  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...37

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