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SN74SSTV32852GKFR PDF预览

SN74SSTV32852GKFR

更新时间: 2024-01-19 06:23:26
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德州仪器 - TI 输出元件输入元件
页数 文件大小 规格书
10页 270K
描述
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

SN74SSTV32852GKFR 数据手册

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SN74SSTV32852  
24-BIT TO 48-BIT REGISTERED BUFFER  
WITH SSTL_2 INPUTS AND OUTPUTS  
SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003  
Member of the Texas Instruments  
Widebus Family  
RESET Input Disables Differential Input  
Receivers, Resets All Registers, and  
Forces All Outputs Low  
1-to-2 Outputs Support Stacked DDR  
DIMMs  
Pinout Optimizes DIMM PCB Layout  
One Device Per DIMM Required  
Supports SSTL_2 Data Inputs  
Outputs Meet SSTL_2 Class II  
Specifications  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Differential Clock (CLK and CLK) Inputs  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
Supports LVCMOS Switching Levels on the  
RESET Input  
description/ordering information  
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V  
operation.  
CC  
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.  
The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing  
of CLK going high and CLK going low.  
The device supports low-power standby operation. When RESET is low, the differential input receivers are  
disabled, and undriven (floating) data, clock, and reference voltage (V  
) inputs are allowed. In addition, when  
REF  
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must  
be held at a valid logic high or low level.  
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in  
the low state during power up.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
PACKAGE  
LFBGA – GKF  
A
0°C to 70°C  
Tape and reel SN74SSTV32852GKFR  
SV852  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74SSTV32852GKFR 替代型号

型号 品牌 替代类型 描述 数据表
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